Advantech Carbon Monoxide Alarm PCI-1718 Series マニュアル

目次

• Chapter 1 Introduction

  10
  • 1.1 Features

    11
  • 1.2 Applications

    12
  • 1.3 Installation Guide

    13
    • Figure 1.1: Installation Flow Chart

      14
  • 1.4 Software Overview

    15
  • 1.5 Device Driver Programming Roadmap

    16
  • 1.6 Accessories

    18
• Chapter 2 Installation

  20
  • 2.1 Unpacking

    20
  • 2.2 Driver Installation

    21
    • Figure 2.1: Setup Screen of Advantech Automation Software

      22
    • Figure 2.2: Different Options for Driver Setup

      22
  • 2.3 Hardware Installation

    23
  • 2.4 Device Setup & Configuration

    24
    • Figure 2.3: The Device Manager Dialog Box

      24
    • Figure 2.4: The Device Setting Dialog Box

      25
    • Figure 2.5: Device Name Appearing on the List of Devices Box

      25
    • Figure 2.6: The Test Utility Dialog Box

      26
• Chapter 3 Signal Connections

  28
  • 3.1 Overview

    28
  • 3.2 Switch and Jumper Settings

    28
    • Figure 3.1: Card Connector, Jumper and Switch Locations

      28
    • 3.2.1 Setting the BoardID Switch (SW1)

      29
      • Board ID Setting (SW1)

        29
    • 3.2.2 Channel Configuration, S/E or DIFF (SW2)

      30
      • Summary of Switch SW2 Settings

        30
    • 3.2.3 D/A Reference Voltage, int./ext. (JP11)

      30
      • Summary of Jumper JP11 Settings

        30
    • 3.2.4 Internal Voltage Reference, -10 V or -5 V (JP10)

      31
      • Summary of Jumper JP10 Settings

        31
    • 3.2.5 Timer Clock Selection (JP8)

      32
      • Summary of Jumper JP8 Settings

        32
    • 3.2.6 Ext. trigger and Counter Gate 0 Control (JP5)

      33
      • Summary of Jumper Settings

        33
    • 3.2.7 Digital Output, 20-pin or 37-pin Connector (JP1)

      33
      • Summary of Jumper Settings

        34
    • 3.2.8 Setting the Time to Reset Digital Outputs

      35
      • JP21 Jumper Settings

        35
  • 3.3 Signal Connections

    36
    • Figure 3.2: I/O Connector Pin Assignments for the PCI-1718 Series

      36
    • 3.3.1 I/O Connector Signal Description

      37
      • I/O Connector Signal Descriptions

        37
    • 3.3.2 Analog Input Connections

      38
      • Figure 3.3: Analog Output Connections

        41
    • 3.3.3 Digital Signal Connections

      42
  • 3.4 Field Wiring Considerations

    43
• Chapter 4 Programming Guide

  46
  • 4.1 Overview

    46
  • 4.2 Programming with the Driver

    46
  • 4.3 Register Programming.

    46
    • 4.3.1 Software Trigger and Polling

      47
    • 4.3.2 Pacer Trigger Mode with Interrupt

      49
    • 4.3.3 Pacer Trigger Mode with Interrupt and FIFO

      53
  • 4.4 Programming with LabVIEW and ActiveDAQ

    57
• Appendix A Specifications

  60
  • A.1 Analog Input

    60
  • A.2 Analog Output

    61
  • A.3 Digital Input

    61
  • A.4 Digital Output

    62
  • A.5 Counter/Timer

    62
  • A.6 General

    63
• Appendix B Block Diagrams

  66
• Appendix C Register Structure & Format

  68
  • C.1 Overview

    68
  • C.2 I/O Port Address Map

    68
    • PCI-1718HDU/HGU Register Format (Part 1)

      69
    • PCI-1718HDU/HGU Register Format (Part 2)

      70
    • PCI-1718HDU/HGU Register Format (Part 3)

      71
  • C.3 A/D Data and Channels - BASE+00H~01H

    72
    • Register for A/D Data and Channels

      72
  • C.4 Software A/D Trigger - BASE+00H

    72
    • Register for Software A/D Trigger

      72
  • C.5 A/D Range Control - BASE+01H

    73
    • Register for A/D Range Control

      73
  • C.6 MUX Scan Channel Control - BASE+02H

    75
    • Register for MUX Scan Channel Control

      75
  • C.7 MUX Scan Channel Status - BASE+02H

    76
    • Register for MUX Scan Channel Status

      76
  • C.8 Digital I/O Registers - BASE + 03/0BH

    76
    • Register for Digital Output

      76
    • Register for Digital Output

      77
  • C.9 D/A Output - BASE+04/05H

    77
    • Register for D/A Output

      77
  • C.10 FIFO Interrupt Control - BASE+06H

    78
    • Register for FIFO Interrupt Control

      78
  • C.11 Clear Interrupt Request - BASE+08H

    79
    • Register for Clear Interrupt Request

      79
  • C.12 A/D Status - BASE+08H

    79
    • Register for A/D Status

      79
  • C.13 A/D Control - BASE+09H

    81
    • Register for A/D Control

      81
  • C.14 Timer/Counter Enable - BASE+0AH

    82
    • Register for Timer/Counter Enable

      82
  • C.15 Programmable Timer/Counter - BASE+0C~0FH

    82
  • C.16 Clear FIFO Interrupt Request - BASE+14H

    83
    • Register for Clear FIFO Interrupt Request

      83
  • C.17 A/D Data and Channel from FIFO - BASE + 17/18H

    83
    • Register for A/D Data and Channel from FIFO

      83
  • C.18 FIFO Status - BASE+19H

    84
    • Register for FIFO Status

      84
  • C.19 FIFO Clear - BASE+19H

    84
    • Register for FIFO Clear

      84
  • C.20 Register Programming Flow Chart

    85
    • C.20.1 Software Trigger Mode with Polling

      85
    • C.20.2 Pacer Trigger Mode with Interrupt

      86
    • C.20.3 Pacer Trigger Mode with Interrupt [FIFO Used]

      87
• Appendix D Calibration

  90
  • D.1 VR Assignment

    91
    • Figure D.1: PCI-1718 VR Assignment

      91
  • D.2 A/D Calibration

    92
  • D.3 D/A Calibration

    93