User ManualTable of ContentsChapter 1 General Description8Chapter 2 Pin Configurations9Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP9Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP10Chapter 3 Block Diagrams11Figure 3.1 Basic Functional Block Diagram11Figure 3.2 Block Diagram12Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram13Chapter 4 Signal Descriptions14Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package)14Chapter 5 Description of Pin Functions15Chapter 6 Signal Description Parameters196.1 Buffer Types19Chapter 7 Functional Description207.1 Clock Generator Block207.2 CSMA/CD Block207.2.1 DMA Block207.2.2 Arbiter Block207.3 MMU Block207.4 BIU Block217.5 MAC-PHY Interface217.5.1 Management Data Software Implementation217.5.2 Management Data Timing227.5.3 MI Serial Port Frame Structure22Figure 7.1 MI Serial Port Frame Timing Diagram237.5.4 MII Packet Data Communication with External PHY24Figure 7.2 MII Frame Format & MII Nibble Order247.6 Serial EEPROM Interface257.7 Internal Physical Layer25Figure 7.3 TX/10BT Frame Format267.7.1 MII Disable277.7.2 Encoder277.7.3 Decoder27Table 7.1 4B/5B Symbol Mapping277.7.4 Clock and Data Recovery297.7.5 Scrambler297.7.6 Descrambler297.7.7 Twisted Pair Transmitter30Figure 7.4 TP Output Voltage Template - 10 MBPS31Table 7.2 Transmit Level Adjust327.7.8 Twisted Pair Receiver33Figure 7.5 TP Input Voltage Template -10MBPS347.7.9 Collision357.7.10 Start of Packet357.7.11 End of Packet36Figure 7.6 SOI Output Voltage Template - 10MBPS377.7.12 Link Integrity & AutoNegotiation37Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP38Figure 7.8 NLP VS. FLP Link Pulse397.7.13 Jabber407.7.14 Receive Polarity Correction407.7.15 Full Duplex Mode417.7.16 Loopback417.7.17 PHY Powerdown417.7.18 PHY Interrupt417.8 Reset42Chapter 8 MAC Data Structures and Registers438.1 Frame Format In Buffer Memory43Figure 8.1 Data Frame Format438.2 Receive Frame Status448.3 I/O Space45Table 8.1 Internal I/O Space Mapping468.4 Bank Select Register468.5 Bank 0 - Transmit Control Register478.6 Bank 0 - EPH Status Register488.7 Bank 0 - Receive Control Register498.8 Bank 0 - Counter Register508.9 Bank 0 - Memory Information Register518.10 Bank 0 - Receive/Phy Control Register518.11 Bank 1 - Configuration Register548.12 Bank 1 - Base Address Register558.13 Bank 1 - Individual Address Registers558.14 Bank 1 - General Purpose Register568.15 Bank 1 - Control Register578.16 Bank 2 - MMU Command Register588.17 Bank 2 - Packet Number Register598.18 Bank 2 - FIFO Ports Register608.19 Bank 2 - Pointer Register618.20 Bank 2 - Data Register628.21 Bank 2 - Interrupt Status Registers62Figure 8.2 Interrupt Structure658.22 Bank 3 - Multicast Table Registers668.23 Bank 3 - Management Interface678.24 Bank 3 - Revision Register678.25 Bank 3 - RCV Register688.26 Bank 7 - External Registers68Chapter 9 PHY MII Registers70Table 9.1 MII Serial Frame Structure71Table 9.2 MII Serial Port Register MAP739.1 Register 0. Control Register749.2 Register 1. Status Register759.3 Register 2&3. PHY Identifier Register76REG769.4 Register 4. Auto-Negotiation Advertisement Register769.5 Register 5. Auto-Negotiation Remote End Capability Register779.6 Register 16. Configuration 1- Structure and Bit Definition789.7 Register 17. Configuration 2 - Structure and Bit Definition799.8 Register 18. Status Output - Structure and Bit Definition809.9 Register 19. Mask - Structure and Bit Definition819.10 Register 20. Reserved - Structure and Bit Definition82Chapter 10 Software Driver and Hardware Sequence Flow8410.1 Software Driver and Hardware Sequence Flow for Power Management84Table 10.1 Typical Flow Of Events For Placing Device In Low Power Mode84Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode8510.2 Typical Flow of Events for Transmit (Auto Release = 0)8510.3 Typical Flow of Events for Transmit (Auto Release = 1)8610.4 Typical Flow of Event For Receive87Figure 10.1 Interrupt Service Routine88Figure 10.2 RX INTR89Figure 10.3 TX INTR90Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected)91Figure 10.5 Drive Send and Allocate Routines92Figure 10.6 Interrupt Generation for Transmit, Receive, MMU94Chapter 11 Board Setup Information95Figure 11.1 64 X 16 Serial EEPROM Map97Chapter 12 Application Considerations98Table 12.1 VL Local Bus Signal Connections98Figure 12.1 LAN91C111 on VL BUS100Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors100Figure 12.2 LAN91C111 on ISA BUS102Table 12.3 EISA 32 Bit Slave Signal Connections102Figure 12.3 LAN91C111 on EISA BUS104Chapter 13 Operational Description10513.1 Maximum Guaranteed Ratings*10513.2 DC Electrical Characteristics10513.3 Twisted Pair Characteristics, Transmit10813.4 Twisted Pair Characteristics, Receive109Chapter 14 Timing Diagrams110Figure 14.1 Asynchronous Cycle - nADS=0110Figure 14.2 Asynchronous Cycle - Using nADS111Figure 14.3 Asynchronous Cycle - nADS=0112Figure 14.4 Asynchronous Ready112Figure 14.5 Burst Write Cycles - nVLBUS=1113Figure 14.6 Burst Read Cycles - nVLBUS=1114Figure 14.7 Address Latching for All Modes115Figure 14.8 Synchronous Write Cycle - nVLBUS=0115Figure 14.9 Synchronous Read Cycle - nVLBUS=0116Figure 14.10 MII Timing117Table 14.1 Transmit Timing Characteristics118Figure 14.11 Transmit Timing118Table 14.2 Receive Timing Characteristics119Figure 14.12 Receive Timing, End of Packet - 10 MBPS119Table 14.3 Collision and Jam Timing Characteristics119Figure 14.13 Collision Timing, Receive120Figure 14.14 Collision Timing, Transmit121Figure 14.15 Jam Timing122Table 14.4 Link Pulse Timing Characteristics123Figure 14.16 Link Pulse Timing124Figure 14.17 FLP Link Pulse Timing125Chapter 15 Package Outlines126Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body126Table 15.1 128 Pin TQFP Package Parameters126Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint127Table 15.2 128 Pin QFP Package Parameters127Chapter 16 Revision History128Table 16.1 Customer Revision History128Size: 1.45 MBPages: 128Language: EnglishOpen manual
User ManualTable of Contents1.1 Audience1Figure 2.1 Detailed Internal Block Diagram23.1 Pin Function Listing3Figure 3.1 BIU Section of functional Block Diagram43.2 ISA Bus43.3 8-Bit Bus4Table 3.1 Single Connection Table43.3.1 Address Decoding Example53.3.2 I/O Base Address 300h Decoding53.4 Asynchronous Interface53.4.1 Typical Signal Connection with Asynchronous Buses63.4.2 Signal Connection with Asynchronous Interfacing7Figure 3.2 Asynchronous Interface Connection73.5 Synchronous Interface (VL-Bus)73.5.1 Typical Connection with Synchronous Interface (VL-Bus)83.5.2 Signal Connection with Synchronous Interfacing9Figure 3.3 Synchronous Interface (VL-Bus) Connection93.5.3 Address Bus93.5.4 AEN93.5.5 W/nR93.5.6 NRDYRTN103.5.7 NSRDY103.5.8 LCLK – Clock Input103.5.9 Reset103.5.10 NBE0-nBE3103.5.11 32-Bit Access and nBE0-nBE3113.5.12 nADS and nCYCLE113.5.13 INTR0113.5.14 Data Bus113.5.15 NLDEV113.6 Timing Analysis11Figure 3.4 Synchronous Write Cycle - nVLBUS=0123.6.1 Write Cycle Address Phase - Cycle Start123.6.2 Write Cycle Data Phase - Cycle End133.6.3 Read Cycle13Figure 3.5 Synchronous Read Cycle - nVLBUS=0133.6.4 Read Cycle Address Phase – Cycle Start143.6.5 Read Cycle Delay Phase143.6.6 Read Cycle Data Phase – Cycle End143.6.7 VL-Burst Mode Operation143.7 Direct Data Register Access interface (nDATACS)143.7.1 The Use of nDATACS153.7.2 Pointer Register15Figure 3.6 Pointer Register153.7.3 Data Register16Figure 3.7 Data Register163.7.4 Timing Analysis Of Direct Access163.8 Asynchronous Read or Write Operation – Non Burst16Figure 3.8 Asynchronous Cycle - nADS=0173.9 Burst Mode Operation Timing – Synchronous Operation173.10 Burst Mode Write Operation18Figure 3.9 Burst Mode Write Operation183.11 Burst Mode Read Operation19Figure 3.10 Burst Mode Read Operation193.12 LAN91C111 Bus Interface203.13 Sample Routine of Performance Measurement and Tuning21Figure 3.11 - Remote End Ping to LAN91C111 Routine224.1 Quartz Crystal234.2 Clock Oscillator244.3 X25OUT244.4 Serial EEPROM Operation244.4.1 INDIVIDUAL ADDRESS 20-22 hex25Table 4.1 EEPROM Memory Map264.4.2 Use the Serial EEPROM as an Option264.4.3 How to Change the IOBASE Address274.5 Power Supply Decoupling274.6 System Power Consumption274.7 Auto Negotiation28Table 4.2 LAN91C111 Auto-Negotiation Mode Register Bit Settings28Table 4.3 - LAN91C111 Manual Configuration Mode Register Bill Settings294.7.1 Initialization Sequence Steps294.8 Power up / Initialization and Powerdown Mode314.9 Loopback314.9.1 EPH Internal Loopback (MAC)314.9.2 Diagnostic Loopback324.9.3 External Loopback324.10 LED Operation344.10.1 LED Description344.11 Thermal Information355.1 Memory Partitioning356.1 Introduction366.2 Definition366.2.1 Big Endian36Table 6.1 Little Endian Memory Images366.2.2 Little Endian36Table 6.2 Little Endian Memory Images376.2.3 Bi-Endian376.3 Implications for the LAN91C111376.4 Physical connections for Big Endian37Figure 6.1 Byte Lane Configuration38Figure 6.2 16-bit Byte Lane Configuration396.5 Software Considerations for Big Endian396.6 Source Code Example406.6.1 Conclusion427.1 Transmit / Receive Interface427.1.1 Transmit Interface42Table 7.1 - TP Transformer Specification427.1.2 Receive Interface427.1.3 Magnetics437.2 RBIAS437.2.1 RBIAS pin437.2.2 TP Transmit Output Current Set437.2.3 Cable Selection44Table 7.2 - Table 7.2 - Cable Configurations447.2.4 Transmitter Droop447.3 MII Management Functions447.3.1 Example Routines To Read and Write the PHY Registers457.4 Multiple Register Access499.1 MAC Register Test509.2 RAM Buffer Test509.3 Transmitting A Packet519.4 Releasing The Transmitted Packet529.5 Receiving A Packet529.6 Releasing A Received Packet529.7 EPH Loopback Test539.8 PHY Loopback Test539.9 External Loopback Test539.10 MMU Test5410.1 91C111 Overview5610.2 New Features and Modification5710.2.1 Receive/PHY Control Register5710.2.2 Memory Information Register5710.2.3 RX_OVRN bit5710.2.4 MDINT Interrupt bit5810.2.5 Internal PHY Registers5810.2.6 Media Independent Interface (MII)5810.2.7 Power Management5810.2.8 Internal PHY and External PHY Selection5810.2.9 General Purpose Output5910.2.10 Reset5910.2.11 Interrupt Pin (INTR0)5910.2.12 SRAM Interface5910.2.13 X25OUT Clock Output Pin5910.2.14 Programmable LED’s5910.2.15 TP Interface5910.2.16 RBIAS pin5910.2.17 Revision Register6010.2.18 Physical Layer Address60Size: 707 KBPages: 60Language: EnglishOpen manual
User ManualTable of ContentsChapter 1 General Description8Chapter 2 Pin Configurations9Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP9Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP10Chapter 3 Block Diagrams11Figure 3.1 Basic Functional Block Diagram11Figure 3.2 Block Diagram12Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram13Chapter 4 Signal Descriptions14Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package)14Chapter 5 Description of Pin Functions15Chapter 6 Signal Description Parameters196.1 Buffer Types19Chapter 7 Functional Description207.1 Clock Generator Block207.2 CSMA/CD Block207.2.1 DMA Block207.2.2 Arbiter Block207.3 MMU Block207.4 BIU Block217.5 MAC-PHY Interface217.5.1 Management Data Software Implementation217.5.2 Management Data Timing227.5.3 MI Serial Port Frame Structure22Figure 7.1 MI Serial Port Frame Timing Diagram237.5.4 MII Packet Data Communication with External PHY24Figure 7.2 MII Frame Format & MII Nibble Order247.6 Serial EEPROM Interface257.7 Internal Physical Layer25Figure 7.3 TX/10BT Frame Format267.7.1 MII Disable277.7.2 Encoder277.7.3 Decoder27Table 7.1 4B/5B Symbol Mapping277.7.4 Clock and Data Recovery297.7.5 Scrambler297.7.6 Descrambler297.7.7 Twisted Pair Transmitter30Figure 7.4 TP Output Voltage Template - 10 MBPS31Table 7.2 Transmit Level Adjust327.7.8 Twisted Pair Receiver33Figure 7.5 TP Input Voltage Template -10MBPS347.7.9 Collision357.7.10 Start of Packet357.7.11 End of Packet36Figure 7.6 SOI Output Voltage Template - 10MBPS377.7.12 Link Integrity & AutoNegotiation37Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP38Figure 7.8 NLP VS. FLP Link Pulse397.7.13 Jabber407.7.14 Receive Polarity Correction407.7.15 Full Duplex Mode417.7.16 Loopback417.7.17 PHY Powerdown417.7.18 PHY Interrupt417.8 Reset42Chapter 8 MAC Data Structures and Registers438.1 Frame Format In Buffer Memory43Figure 8.1 Data Frame Format438.2 Receive Frame Status448.3 I/O Space45Table 8.1 Internal I/O Space Mapping468.4 Bank Select Register468.5 Bank 0 - Transmit Control Register478.6 Bank 0 - EPH Status Register488.7 Bank 0 - Receive Control Register498.8 Bank 0 - Counter Register508.9 Bank 0 - Memory Information Register518.10 Bank 0 - Receive/Phy Control Register518.11 Bank 1 - Configuration Register548.12 Bank 1 - Base Address Register558.13 Bank 1 - Individual Address Registers558.14 Bank 1 - General Purpose Register568.15 Bank 1 - Control Register578.16 Bank 2 - MMU Command Register588.17 Bank 2 - Packet Number Register598.18 Bank 2 - FIFO Ports Register608.19 Bank 2 - Pointer Register618.20 Bank 2 - Data Register628.21 Bank 2 - Interrupt Status Registers62Figure 8.2 Interrupt Structure658.22 Bank 3 - Multicast Table Registers668.23 Bank 3 - Management Interface678.24 Bank 3 - Revision Register678.25 Bank 3 - RCV Register688.26 Bank 7 - External Registers68Chapter 9 PHY MII Registers70Table 9.1 MII Serial Frame Structure71Table 9.2 MII Serial Port Register MAP739.1 Register 0. Control Register749.2 Register 1. Status Register759.3 Register 2&3. PHY Identifier Register76REG769.4 Register 4. Auto-Negotiation Advertisement Register769.5 Register 5. Auto-Negotiation Remote End Capability Register779.6 Register 16. Configuration 1- Structure and Bit Definition789.7 Register 17. Configuration 2 - Structure and Bit Definition799.8 Register 18. Status Output - Structure and Bit Definition809.9 Register 19. Mask - Structure and Bit Definition819.10 Register 20. Reserved - Structure and Bit Definition82Chapter 10 Software Driver and Hardware Sequence Flow8410.1 Software Driver and Hardware Sequence Flow for Power Management84Table 10.1 Typical Flow Of Events For Placing Device In Low Power Mode84Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode8510.2 Typical Flow of Events for Transmit (Auto Release = 0)8510.3 Typical Flow of Events for Transmit (Auto Release = 1)8610.4 Typical Flow of Event For Receive87Figure 10.1 Interrupt Service Routine88Figure 10.2 RX INTR89Figure 10.3 TX INTR90Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected)91Figure 10.5 Drive Send and Allocate Routines92Figure 10.6 Interrupt Generation for Transmit, Receive, MMU94Chapter 11 Board Setup Information95Figure 11.1 64 X 16 Serial EEPROM Map97Chapter 12 Application Considerations98Table 12.1 VL Local Bus Signal Connections98Figure 12.1 LAN91C111 on VL BUS100Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors100Figure 12.2 LAN91C111 on ISA BUS102Table 12.3 EISA 32 Bit Slave Signal Connections102Figure 12.3 LAN91C111 on EISA BUS104Chapter 13 Operational Description10513.1 Maximum Guaranteed Ratings*10513.2 DC Electrical Characteristics10513.3 Twisted Pair Characteristics, Transmit10813.4 Twisted Pair Characteristics, Receive109Chapter 14 Timing Diagrams110Figure 14.1 Asynchronous Cycle - nADS=0110Figure 14.2 Asynchronous Cycle - Using nADS111Figure 14.3 Asynchronous Cycle - nADS=0112Figure 14.4 Asynchronous Ready112Figure 14.5 Burst Write Cycles - nVLBUS=1113Figure 14.6 Burst Read Cycles - nVLBUS=1114Figure 14.7 Address Latching for All Modes115Figure 14.8 Synchronous Write Cycle - nVLBUS=0115Figure 14.9 Synchronous Read Cycle - nVLBUS=0116Figure 14.10 MII Timing117Table 14.1 Transmit Timing Characteristics118Figure 14.11 Transmit Timing118Table 14.2 Receive Timing Characteristics119Figure 14.12 Receive Timing, End of Packet - 10 MBPS119Table 14.3 Collision and Jam Timing Characteristics119Figure 14.13 Collision Timing, Receive120Figure 14.14 Collision Timing, Transmit121Figure 14.15 Jam Timing122Table 14.4 Link Pulse Timing Characteristics123Figure 14.16 Link Pulse Timing124Figure 14.17 FLP Link Pulse Timing125Chapter 15 Package Outlines126Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body126Table 15.1 128 Pin TQFP Package Parameters126Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint127Table 15.2 128 Pin QFP Package Parameters127Chapter 16 Revision History128Table 16.1 Customer Revision History128Size: 1.45 MBPages: 128Language: EnglishOpen manual