SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
103
Revision 1.22 (09-25-08)
DATASHEET
4.3
DMAC Control and Status Registers (DCSR)
lists the registers contained in this section.
Table 4.4 DMAC Control and Status Register (DCSR) Map
OFFSET
SYMBOL
REGISTER NAME
0000h
BUS_MODE
Bus Mode Register
0004h
TX_POLL_DEMAND
Transmit Poll Demand Register
0008h
RX_POLL_DEMAND
Receive Poll Demand Register
000Ch
RX_ BASE_ADDR
Receive List Base Address Register
0010h
TX_BASE_ADDR
Transmit List Base Address Register
0014h
DMAC_STATUS
DMA Controller Status Register
0018h
DMAC_CONTROL
DMA Controller Control (Operation Mode) Register
001Ch
DMAC_INTR_ENA
DMA Controller Interrupt Enable Register
0020h
MISS_FRAME_CNTR
Missed Frame Counter (RX Only)
0024h – 004Ch
RESERVED
Reserved for future expansion
0050h
CUR_TX_BUF_ADDR
Current Transmit Buffer Address
0054h
CUR_RX_BUF_ADDR
Current Receive Buffer Address
0058h – 007Ch
RESERVED
Reserved for future expansion