SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
107
Revision 1.22 (09-25-08)
DATASHEET
4.3.4
Receive List Base Address Register (RX_BASE_ADDR)
This register specifies the start address of the receive buffer list. RX_BASE_ADDR must be 4-DWORD
(16 byte) aligned (e.g. Reserved address bits 3:0 must be 0).
(16 byte) aligned (e.g. Reserved address bits 3:0 must be 0).
Offset:
000Ch
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:4
Start of Receive List (SRL)
This field points to the start of the receive buffer descriptor list. The
descriptor list resides in the Host memory. Writing this register is only valid
when the RX DMA engine is in the stopped state. When stopped, this
register must be written before the START command is given.
This field points to the start of the receive buffer descriptor list. The
descriptor list resides in the Host memory. Writing this register is only valid
when the RX DMA engine is in the stopped state. When stopped, this
register must be written before the START command is given.
R/W
28‘h0
3:0
RESERVED
RO
-