SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
113
Revision 1.22 (09-25-08)
DATASHEET
4.3.8
DMA Controller Interrupt Enable
Register (DMAC_INTR_ENA)
This register enables the DMAC interrupts reported in the DMAC_STATUS register. Setting a bit to 1
enables the corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
enables the corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Offset:
001Ch
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:17
RESERVED
RO
-
16
Normal Interrupt Summary Enable (NIS_EN)
When set, normal interrupt is enabled. When reset, no normal interrupt is
enabled. This bit enables the following bits:
When set, normal interrupt is enabled. When reset, no normal interrupt is
enabled. This bit enables the following bits:
DMAC_STATUS[0]: Transmit interrupt (TI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
R/W
0b
15
Abnormal Interrupt Summary Enable (AIS_EN)
When set, abnormal interrupt is enabled. When reset, no abnormal interrupt
is enabled. This bit enables the following bits:
When set, abnormal interrupt is enabled. When reset, no abnormal interrupt
is enabled. This bit enables the following bits:
DMAC_STATUS[1]: Transmit process stopped (TPS)
DMAC_STATUS[5]: RESERVED
DMAC_STATUS[7]: Receive buffer unavailable (RU)
DMAC_STATUS[8]: Receive process stopped (RPS)
DMAC_STATUS[5]: RESERVED
DMAC_STATUS[7]: Receive buffer unavailable (RU)
DMAC_STATUS[8]: Receive process stopped (RPS)
R/W
0b
14
RESERVED
R/W
0b
13:11
RESERVED
RO
-
10
RESERVED
R/W
0b
9
Receive Watchdog Timeout (RWT_EN)
The Receive Watchdog Timeout is enabled only when this bit and the
Abnormal Interrupt Summary Enable bit (bit [15]) are set.
The Receive Watchdog Timeout is enabled only when this bit and the
Abnormal Interrupt Summary Enable bit (bit [15]) are set.
R/W
0b
8
Receive Process Stopped (RPS_EN)
The Receive Process Stopped Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
The Receive Process Stopped Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
R/W
0b
7
Receive Buffer Unavailable (RU_EN)
The Receive Buffer Unavailable Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
The Receive Buffer Unavailable Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
R/W
0b
6
Receive Interrupt (RI_EN)
The Receive Interrupt is enabled only when this bit and the Abnormal
Interrupt Summary Enable bit (bit [15]) are set.
The Receive Interrupt is enabled only when this bit and the Abnormal
Interrupt Summary Enable bit (bit [15]) are set.
R/W
0b
5
RESERVED
R/W
0b
4:3
RESERVED
RO
-
2
Transmit Buffer Unavailable (TU_EN)
The Transmit Buffer Unavailable Interrupt is enabled only when this bit and
the Normal Interrupt Summary Enable bit (bit [16]) are set.
The Transmit Buffer Unavailable Interrupt is enabled only when this bit and
the Normal Interrupt Summary Enable bit (bit [16]) are set.
R/W
0b