SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
124
SMSC LAN9420/LAN9420i
DATASHEET
4.4.3
MAC Address Low Register (ADDRL)
This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the
first octet of the Ethernet frame.
first octet of the Ethernet frame.
below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
reception of the Ethernet physical address.
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and
ADDRH registers would be programmed as shown in
ADDRH registers would be programmed as shown in
. The values required to automatically
load this configuration from the EEPROM are shown in
Offset:
0088h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Physical Address [31:0]
This field contains the lower 32 bits (32:0) of the Physical Address of this
MAC device.
This field contains the lower 32 bits (32:0) of the Physical Address of this
MAC device.
R/W
32‘hF
Table 4.6 ADDRL, ADDRH Byte Ordering
ADDRL, ADDRH
ORDER OF RECEPTION ON ETHERNET
ADDRL[7:0]
1
st
ADDRL[15:8]
2
nd
ADDRL[23:16]
3
rd
ADDRL[31:24]
4
th
ADDRH[7:0]
5
th
ADDRH[15:8]
6
th
Figure 4.2 Example ADDRL, ADDRH Address Ordering
0x12
0
7
0x34
8
15
0x56
16
23
0x78
24
31
ADDRL
0x9A
0
7
0xBC
8
15
ADDRH
xx
16
23
xx
24
31