SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
49
Revision 1.22 (09-25-08)
DATASHEET
Transmit Descriptor 2 (TDES2)
Transmit Descriptor 3 (TDES3)
3.4.3
Initialization
The following sequence explains the initialization steps for the DMA controller and activation of the
receive and transmit paths:
receive and transmit paths:
1. Configure the BUS_MODE register.
2. Mask unnecessary interrupts by writing to the DMAC_INTR_ENA register.
3. Software driver writes to descriptor base address registers RX_BASE_ADDR and
TX_BASE_ADDR after the RX and TX descriptor lists are created.
4. Write DMAC_CONTROL to set bits 13 (ST) and 1 (SR) to start the TX and RX DMA. The TX and
RX engines enter the running state and attempt to acquire descriptors from the respective
descriptor lists. The receive and transmit engines begin processing receive and transmit
operations.
descriptor lists. The receive and transmit engines begin processing receive and transmit
operations.
5. Set bit 2 (RXEN) of MAC_CR to turn the receiver on.
6. Set bit 3 (TXEN) of MAC_CR to turn the transmitter on.
Table 3.11 TDES2 Bit Fields
BITS
DESCRIPTION
31:0
Buffer 1 Address Pointer
This is the physical address of buffer 1. There are no limitations on the buffer address alignment.
This is the physical address of buffer 1. There are no limitations on the buffer address alignment.
Host Actions: Initializes this field.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.
Table 3.12 TDES3 Bit Fields
BITS
DESCRIPTION
31:0
Buffer 2 Address Pointer (Next Descriptor Address)
The TCH (Second Address Chained) bit (TDES1[24]) determines the usage of this field as
follows:
The TCH (Second Address Chained) bit (TDES1[24]) determines the usage of this field as
follows:
TCH is zero: This field contains the pointer to the address of buffer 2 in Host memory. There
are no limitations on buffer address alignment.
are no limitations on buffer address alignment.
TCH is one: Descriptor chaining is in use and this field contains the pointer to the next
descriptor in Host memory. The descriptor must be 4-DWORD (16-byte) aligned (TDES3[3:0] =
0000b). In the case where the buffer is not 4-DWORD aligned, the resulting behavior is
undefined.
descriptor in Host memory. The descriptor must be 4-DWORD (16-byte) aligned (TDES3[3:0] =
0000b). In the case where the buffer is not 4-DWORD aligned, the resulting behavior is
undefined.
Note:
If TER (TDES1[25]) is set, TCH is ignored and this field is treated as a pointer to buffer
2 as in the “TCH is zero” case above.
2 as in the “TCH is zero” case above.
Host Actions: Initializes this field.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.