SMSC LAN9420i Manual De Usuario

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Revision 1.22 (09-25-08)

74

SMSC LAN9420/LAN9420i

the nPME signal upon detection of various power management events, such as an Ethernet “Wake On
LAN”, or upon detection of an Ethernet link status change. 

As a result of the nPME assertion by the device, the PCI Host can reconfigure the power management
state. This mechanism is used, for example, when LAN9420/LAN9420i is in low power mode and must
be restored to a functional state, as a result of the detection of “Wake On LAN” event. The Host can
respond to the subsequent nPME assertion by changing the 

bits in the 

 to restore

LAN9420/LAN9420i to the D0 state.

As a single function device, LAN9420/LAN9420i implements a 

 and a 

, which

are mapped into the PCI configuration space at addresses 78h and 7Ch, respectively. The 

 field of the PCI_PMC register is dependant on the

setting of the external 

 pin. The Data_Scale and Data_Select fields of the PCI_PMCSR

register will always return zero, as the Data Register is not implemented.

LAN9420/LAN9420i complies with Revision 1.1 of the PCI Bus Power Management Interface
Specification, V2.0 of the Network Device Class Specification and Revision 3.0 of the Advanced
Configuration and Power Interface Specification (ACPI specification).

Refer to 

 for power consumption in the various power

management states.

The following external signals are provided in support of PCI power management:

„

nPME: LAN9420/LAN9420i can assert this signal upon detection of an enabled power management 
event. 

Note: The nPME signal requires external isolation if the system supports wake from B3 and the

LAN9420/LAN9420i’s VAUXDET=0 (i.e., the system is powered, but LAN9420/LAN9420i is not)

„

VAUXDET: This signal enables LAN9420/LAN9420i’s ability to detect power management events 
and assert nPME from the D3

COLD

 state (wake from D3

COLD

). When tied to the PCI system’s 

3.3Vaux power supply, wake from D3

COLD

 is enabled. When tied to ground, wake from D3

COLD

 is 

disabled.

„

PWRGOOD: If VAUXDET is low (wake from D3

COLD

 is disabled) PWRGOOD must be tied to +3.3V 

power. If VAUXDET is connected to 3.3Vaux (wake from D3

COLD

 is enabled), LAN9420/LAN9420i 

uses PWRGOOD to determine the state of the system’s +3.3V power supply. When VAUXDET is 
high, the device is isolated from the PCI bus when PWRGOOD is deasserted and will ignore all 
PCI transactions, including PCICLK and PCInRST.

LAN9420/LAN9420i requires the following external 3.3V power supplies: 

„

VDD33IO, VDD33A, VDD33BIAS

The connection of the device’s 3.3V power pins varies depending on the requirement for support of
wake from D3

COLD

. If wake from D3

COLD

 is enabled (VAUXDET is connected to 3.3Vaux), the 3.3V

power pins must be connected to the PCI system’s 3.3Vaux power supply. If wake from D3

COLD

 is

disabled, (VAUXDET is connected to VSS), the 3.3V power pins must be connected to the system’s
+3.3V power. Please refer to 

 for more

information on the LAN9420/LAN9420i power supplies.

Note: The LAN9420/LAN9420i device also requires 1.8V, but this is supplied by an internal regulator

and connection does not vary. Since the 1.8V supply is derived from VDD33IO, there is no
need to discuss it separately.