SMSC LAN9420i Manual De Usuario

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

SMSC LAN9420/LAN9420i

79

Revision 1.22 (09-25-08)

The LAN9420/LAN9420i device employs the following resets:

„

Power-On Reset (POR): This reset is asserted on initial application of device power. If the device 
is powered from the PCI auxiliary power supply, this reset is asserted for approximately 21mS after 
3.3Vaux has reached its operational level. If the device is not powered from the auxiliary supply, 
this reset is asserted for approximately 21mS after the main PCI 3.3V supply has reached its 
operational level.

„

PCInRST: This is the active-low reset input from the PCI bus. In the D0

U

 or D0

A

 states, the device 

is reset when PCInRST is low. In the D3

HOT

 or D3

COLD 

states, the device is reset on the 

deassertion (low-to-high transition) of PCInRST.

„

D3 Transition Reset (D3RST): This reset occurs when transitioning from the D3

HOT 

to D0

U

 states.

„

Software Reset (SRST): This reset is initiated by setting the 

 bit in the 

. Software Reset does not clear control register bits marked as NASR.

„

PHY Reset via PMT_CTRL (PHY_RST): This reset is asserted by setting the 

 in the 

. Refer to section 

 for more information.

„

PHY Soft Reset (PHY_SRST): This reset is asserted by writing a ‘1’ to bit 15 of the PHY’s Basic 
Control Register. Refer to section 

The reset map in 

 shows the conditions under which various modules within

LAN9420/LAN9420i are reset.

PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3

COLD

wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support
D3

COLD 

wake. 

Software Reset does not clear control register bits marked as NASR.

If PHY was reset on entry to the D3

HOT

, it will be reset when exiting the D3

HOT

. If the PHY

was not reset on entry to the D3

HOT

, it will not be reset when exiting D3

HOT

.

The 

 

 registers (optionally

loaded from the EEPROM) are not reset during this transition.

PCI PME Logic

X

PHY

(

X

X

X

X

(

)

EEPROM Load

X

X

PCI Configuration 

Registers 

(except PME registers)

X

X

X

)

MAC

X

X

X

X

TX/RX DMACS

X

X

X

X

SCSR

X

X

X

X

(

)