SMSC LAN9420i Manual De Usuario

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Revision 1.22 (09-25-08)

SMSC LAN9420/LAN9420i

DATASHEET

4.2

System Control and Status Registers (SCSR)

Table 4.2, "System Control and Status Register Addresses"

lists the registers contained in this section.

Table 4.2 System Control and Status Register Addresses

OFFSET

SYMBOL

REGISTER NAME

00C0h

ID_REV

ID and Block Revision

00C4h

INT_CTL

Interrupt Control Register

00C8h

INT_STS

Interrupt Status Register

00CCh

INT_CFG

Interrupt Configuration Register

00D0h

GPIO_CFG

General Purpose IO Configuration

00D4h

GPT_CFG

General Purpose Timer Configuration

00D8h

GPT_CNT

General Purpose Timer Current Count

00DCh

BUS_CFG

System Bus Configuration Register

00E0h

PMT_CTRL

Power Management Control

00E4h – 00F0h

RESERVED

Reserved for Future Use

00F4h

FREE_RUN

Free Run Counter

00F8h

E2P_CMD

EEPROM Command Register

00FCh

E2P_DATA

EEPROM Data Register

The registers located at 0100h - 01FCh are visible via the memory map, but are reserved and must not be

accessed. The registers located at 0100h - 01FCh are not visible or accessible via IO.

0100h – 01FCh

RESERVED

Reserved for Future Use