STMicroelectronics Discovery kit for STM32L151/152 line - with STM32L152RC MCU STM32L152C-DISCO STM32L152C-DISCO Hoja De Datos

DocID022799 Rev 6

Two complementary static tests are required on six parts to assess the latch-up 
performance: 


A supply overvoltage is applied to each power supply pin



A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

          

As a general rule, current injection to the I/O pins, due to external voltage below V

SS

 or 

above V

DD

 (for standard pins) should be avoided during normal product operation. 

However, in order to give an indication of the robustness of the microcontroller in cases 
when abnormal injection accidentally happens, susceptibility tests are performed on a 
sample basis during device characterization.

While a simple application is executed on the device, the device is stressed by injecting 
current into the I/O pins programmed in floating input mode. While current is injected into 
the I/O pin, one at a time, the device is checked for functional failures. 

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher 
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out 
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator 
frequency deviation, LCD levels).

The test results are given in the 

.

          

LU

Static latch-up class

T

A 

+105 °C conforming to JESD78A

II level A

I

INJ

Injected current on all 5 V tolerant (FT) pins

-5 

(1)

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject 

negative currents.

+0

mA

Injected current on any other pin

-5 

+5