STMicroelectronics Discovery kit for STM32L151/152 line - with STM32L152RC MCU STM32L152C-DISCO STM32L152C-DISCO Hoja De Datos

DocID022799 Rev 6

The STM32L15xxC product line I

2

C interface meets the requirements of the standard I

2

C 

communication protocol with the following restrictions: SDA and SCL are not “true” open-
drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin 
and V

DD 

is disabled, but is still present.

The I

2

C characteristics are described in 

. Refer also to 

 for more details on the input/output alternate function characteristics (SDA 

and SCL).

          

1. Guaranteed by design, not tested in production.

2. f

PCLK1

 

must be at least 2 MHz to achieve standard mode I

²

C frequencies. It must be at least 4 MHz to 

achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast 

mode clock.

t

w(SCLL)

SCL clock low time

4.7

-

1.3 

-

µs

t

w(SCLH)

SCL clock high time

4.0

-

0.6 

-

t

su(SDA)

SDA setup time

250

-

100 

-

ns

t

h(SDA)

SDA data hold time

-

3450

-

900

(3)

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL 

signal.

t

r(SDA)

t

r(SCL)

SDA and SCL rise time

-

1000

-

300

t

f(SDA)

t

f(SCL)

SDA and SCL fall time

-

300

-

300 

t

h(STA)

Start condition hold time

4.0

-

0.6

-

µs

t

su(STA)

Repeated Start condition 
setup time

4.7

-

0.6 -

t

su(STO)

Stop condition setup time

4.0

-

0.6 

-

s

t

w(STO:STA)

Stop to Start condition time 
(bus free)

4.7

-

1.3

-

s

C

b

Capacitive load for each bus 
line

-

400

-

400

pF

t

SP

Pulse width of spikes that 
are suppressed by the 
analog filter

0

50

(4)

4. The minimum width of the spikes filtered by the analog filter is above t

SP(max)

. 

0

50

ns