STMicroelectronics Discovery kit for STM32L151/152 line - with STM32L152RC MCU STM32L152C-DISCO STM32L152C-DISCO Hoja De Datos

DocID022799 Rev 6

Unless otherwise specified, the parameters given in the following table are derived from 
tests performed under ambient temperature, f

PCLKx 

frequency and V

DD

 supply voltage 

conditions summarized in 

.

Refer to 

 for more details on the 

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

          

f

SCK

1/t

c(SCK)

SPI clock frequency

Master mode

-

16

MHz

Slave mode

-

16

Slave transmitter

-

12

(3)

t

r(SCK)

t

f(SCK)

SPI clock rise and fall time

Capacitive load: C = 30 pF

-

 6

ns

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode

30

70

%

t

su(NSS)

NSS setup time 

Slave mode

4t

HCLK

-

ns

t

h(NSS)

NSS hold time

Slave mode

2t

HCLK

-

t

w(SCKH)

t

w(SCKL)

SCK high and low time

Master mode

t

SCK

/2

5 t

SCK

/2+3

t

su(MI)

Data input setup time

Master mode

5

-

t

su(SI)

Slave mode

6

-

t

h(MI)

Data input hold time

Master mode

5

-

t

h(SI)

Slave mode

5

-

t

a(SO)

(4)

Data output access time

Slave mode

 0

3t

HCLK

t

Data output valid time

Slave mode

-

 33

t

Data output valid time

Master mode

-

 6.5

t

h(SO)

Data output hold time

Slave mode

 17

-

t

h(MO)

Master mode

 0.5

-

1. The characteristics above are given for voltage range 1.

2. Based on characterization, not tested in production.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) 

ranging between 40 to 60%. 

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.