Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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10. Programming
Interface
The Graphics Controller (GC) contains an extensive set of registers and instructions (also referred to as
“Commands”) for controlling 2D, 3D, and video operations. This section describes the programmer’s
interface to these registers and instructions.
“Commands”) for controlling 2D, 3D, and video operations. This section describes the programmer’s
interface to these registers and instructions.
10.1.
Reserved Bits and Software Compatibility
In many registers, instruction and memory layout descriptions, certain bits are marked as "Reserved".
When bits are marked as reserved, it is essential for compatibility with future devices that software treat
these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded
as not only undefined, but also unpredictable. Software should follow these guidelines in dealing with
reserved bits:
When bits are marked as reserved, it is essential for compatibility with future devices that software treat
these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded
as not only undefined, but also unpredictable. Software should follow these guidelines in dealing with
reserved bits:
Do not depend on the states of any reserved bits when testing values of registers that contain such bits.
Mask out the reserved bits before testing. Do not depend on the states of any reserved bits when storing
to instruction or to a register.
Mask out the reserved bits before testing. Do not depend on the states of any reserved bits when storing
to instruction or to a register.
When loading a register or formatting an instruction, always load the reserved bits with the values
indicated in the documentation or zero.
indicated in the documentation or zero.
10.2. Overview
The GC is programmed via three basic mechanisms.
POST-Time Programming of PCI Configuration Registers
These registers are programmed once during POST of the video device. The PCI Configuration registers
are not covered in this PRM. For details on accessing the graphics controller’s PCI configuration space,
refer to the Intel
are not covered in this PRM. For details on accessing the graphics controller’s PCI configuration space,
refer to the Intel
®
815 Chipset: 82815 Graphics and Memory Controller Hub EDS. For additional
information on accessing non-PCI registers refer to the System Address Map chapter.
Direct (Physical I/O and/or Memory-Mapped I/O) Access of GC Registers
Various GC functions can only be controlled via direct register access. In addition, direct register access
is required to initiate the (asynchronous) execution of GC instruction streams. This programming
mechanism is "direct" and synchronous with software execution on the processor.
is required to initiate the (asynchronous) execution of GC instruction streams. This programming
mechanism is "direct" and synchronous with software execution on the processor.
Instruction Stream DMA (via Instruction Ring Buffers)
This programming mechanism utilizes the indirect (and asynchronous) execution of GC instruction
streams to control certain GC functions (e.g., all 2D and 3D drawing operations). Software writes
instructions into an instruction buffer (either a Ring Buffer or Batch Buffer) and informs the GC that the
instructions are ready for execution. The Instruction Parser will then (at some point) read the instructions
via DMA and execute them.
streams to control certain GC functions (e.g., all 2D and 3D drawing operations). Software writes
instructions into an instruction buffer (either a Ring Buffer or Batch Buffer) and informs the GC that the
instructions are ready for execution. The Instruction Parser will then (at some point) read the instructions
via DMA and execute them.