Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
143
10.4.3. Instruction
Parser
The following figure shows a high-level diagram of the GC instruction interface. The GC's Instruction
Parser (IP) unit is responsible for:
Parser (IP) unit is responsible for:
• Detecting the presence of instructions (within the Ring Buffers)
• Arbitrating the execution of instruction streams
• Reading instructions from Ring Buffers and Batch Buffers via DMA
• Parsing the common "Client" (destination) field of instructions
• Execution of Instruction Parser instructions (which control IP functionality, provide synchronization
• Arbitrating the execution of instruction streams
• Reading instructions from Ring Buffers and Batch Buffers via DMA
• Parsing the common "Client" (destination) field of instructions
• Execution of Instruction Parser instructions (which control IP functionality, provide synchronization
functions as well as provide miscellaneous GC control functions)
• Redirection of 2D and 3D instructions to the appropriate destination while following drawing engine
concurrency and coherency rules
Figure 26.
Graphics Controller Instruction Interface
DMA
FIFO
FIFO
Instr
Parser
3D Instructions (3D state,
3D Primitives, STRBLT,
Motion Compensation)
3D Primitives, STRBLT,
Motion Compensation)
2D Instructions
cmd_str.vsd
3D
Engine
BLT
Engine
Instruction access and decoding
Low Priority Ring
(Graphics Memory)
Instruction
Batch Buff Instr
Batch Buffers
Instruction
- Parser Control
(e.g., Batch Buffer Instr., NOP,
Sync ID, Flush, breakpoint )
(e.g., Batch Buffer Instr., NOP,
Sync ID, Flush, breakpoint )
- Memory Interface Control
(e.g., Store DWord to memory)
(e.g., Store DWord to memory)
- Display/Overlay Control
(e.g., Front Buffer, Scan
Lines, Overlay Flip
(e.g., Front Buffer, Scan
Lines, Overlay Flip
Instruction Parser Instructions
Display
Engine
Overlay
Engine
Interrupt Ring
(Graphics Memory)
Instruction
Batch Buff Instr
Instruction
Batch Buffers
DMA
DMA