Intel 815 Manuel D’Utilisation

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buffers, and the impact on latency and performance, should be carefully considered by software 
developers. 

The IP performs arbitration for instruction execution at the following points: 

•  Continuously when idle (i.e., no pending instructions) 
•  Between instructions in the LPRB 
•  After GFXCMDPARSER_BATCH_BUFFER instructions when executed from the LPRB or at the 

end of an LP batch buffer 

•  Upon execution of a wait instruction in the IRB (if a wait is required) 

Software must consider the consequences of the IP redirecting instruction execution at these arbitration 
points. That is, software needs to coordinate the use and control of the instruction stream sources such 
that GC operations proceed in the intended order and with the intended GC state. For example, software 
must prevent the case where instructions placed in the IRB interrupt the LP instruction stream and 
invalidate a GC state required by the pending LP stream. 

At an arbitration point, the IP will consider the current state of instruction execution (i.e., Low Priority vs 
Interrupt, Ring vs. Batch) along with the current state of the RBs and possibly pending wait events. The 
IP will then determine how to proceed with execution, given that status information and the following 
instruction stream priorities (highest priority to lowest):  

1.  Next instruction in batch buffer (regardless of initiating ring buffer) 
2.  Next instruction pending in IRB (assuming IRB arbitration is enabled) 
3.  Initiation of LP batch buffer (including resumption of interrupted LP batch chain) 
4.  Next instruction pending in LPRB 

To ensure that the graphics controller does not corrupt system memory or graphics memory through 
invalid instructions from a batch buffer sequence, the batch buffer instruction has a flag that can be set to 
indicate that it is from a non-trusted source.  

When the IP processes a non-trusted batch buffer from one of the ring buffers, it does not allow any 
immediate store DWord instructions, because this instruction causes writes to system memory, not 
gathered through the GTT. The protection mode (Protected or Unprotected) is set in the batch buffer 
instruction that is in the ring buffer. The protection mode set persists throughout the batch buffer 
sequence; including batch buffers that are chained. Thus, a chained batch buffer cannot re-enable writes 
to system memory. 

If the IP detects an instruction that is disallowed in protected mode, it stores the header of the instruction, 
the origin of the instruction, and an error code. In addition, such an event can generate an interrupt or a 
hardware write to system memory, if enabled and unmasked. At this point the IP, can only be reactivated 
by a reset.