Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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10.5. Instruction
Format
GC instructions are defined with various formats. The first DWord of all instructions is called the header
DWord. The header contains the only field common to all instructions: the client field that determines the
major GC unit that will process the instruction data. The Instruction Parser examines the client field of
each instruction to condition the further processing of the instruction and route the instruction data
accordingly. Valid client values are:
DWord. The header contains the only field common to all instructions: the client field that determines the
major GC unit that will process the instruction data. The Instruction Parser examines the client field of
each instruction to condition the further processing of the instruction and route the instruction data
accordingly. Valid client values are:
• Instruction Parser (00h)
• 2D Processor (02h)
• 3D Processor (03h)
• 2D Processor (02h)
• 3D Processor (03h)
GC instructions vary in length, though are always multiples of DWords. The length of an instruction is
either:
either:
• implied by the client/opcode
• fixed by the client/opcode yet included in a header field (so the IP explicitly knows how much data
• fixed by the client/opcode yet included in a header field (so the IP explicitly knows how much data
to copy/process)
• variable, with a field in the header indicating the total length of the instruction
Note that GC instruction sequences require QWord alignment and padding to QWord length to be placed
in Ring and Batch Buffers.
in Ring and Batch Buffers.
The following subsections provide a brief overview of the GC instructions by client type. Figure 29
provides a diagram of the formats of the header DWords for all GC instructions. Table 13 provides a list
of instruction mnemonics by client type.
provides a diagram of the formats of the header DWords for all GC instructions. Table 13 provides a list
of instruction mnemonics by client type.
10.5.1. Instruction Parser Instructions
Instruction Parser (IP) instructions are basically those instructions which do not require processing by the
2D or 3D Rendering/Mapping engines. The functions performed by these instructions include:
2D or 3D Rendering/Mapping engines. The functions performed by these instructions include:
• Control of the instruction stream (e.g., Batch Buffer commands, breakpoints, ARB On/Off, etc.)
• Hardware synchronization (e.g., flush, wait-for-event)
• Software synchronization (e.g., Store DWORD, report head)
• Graphics buffer definition (e.g., Display buffer, Overlay buffer, 3D Destination and Z buffer)
• Miscellaneous functions
• Hardware synchronization (e.g., flush, wait-for-event)
• Software synchronization (e.g., Store DWORD, report head)
• Graphics buffer definition (e.g., Display buffer, Overlay buffer, 3D Destination and Z buffer)
• Miscellaneous functions
Refer to the Instruction Parser Instructions Chapter for a description of these instructions.
10.5.2. 2D
Instructions
The 2D instructions include various flavors of Blt operations, along with instructions to set up the Blt
engine state without actually performing a Blt. Most instructions are of fixed length, though there are a
few instructions that include a variable amount of inline data at the end of the instruction. Refer to the 2D
Instructions Chapter for a description of these instructions.
engine state without actually performing a Blt. Most instructions are of fixed length, though there are a
few instructions that include a variable amount of inline data at the end of the instruction. Refer to the 2D
Instructions Chapter for a description of these instructions.