Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
155
11.2.4. GFXCMDPARSER_WAIT_FOR_EVENT
This instruction can be used to pause instruction stream processing until a specific event occurs. Only
one event can be specified -- specifying multiple events is UNDEFINED. The effect of the wait operation
depends on the source of the instruction. If executed from a batch buffer, the instruction parser halts (and
suspend instruction arbitration) until the event occurs. If executed from a ring buffer, further processing
of that ring will be suspended, although instruction arbitration (from other rings) will continue.
one event can be specified -- specifying multiple events is UNDEFINED. The effect of the wait operation
depends on the source of the instruction. If executed from a batch buffer, the instruction parser halts (and
suspend instruction arbitration) until the event occurs. If executed from a ring buffer, further processing
of that ring will be suspended, although instruction arbitration (from other rings) will continue.
DWord Bit
Description
0 31:29
Client: 000 – Instruction Parser
28:23
Opcode: 03h
22:4
Reserved: 0000h
3
VBLANK: If this bit is set, and this instruction is executed out of a Batch Buffer, the
Parser halts when it parses this instruction until the beginning of the next display vertical
blank. If executed out of a ring buffer, the Parser sets a flag that eliminates that ring
from the arbitration until the flag is cleared. This flag is cleared by the appropriate ed
Parser halts when it parses this instruction until the beginning of the next display vertical
blank. If executed out of a ring buffer, the Parser sets a flag that eliminates that ring
from the arbitration until the flag is cleared. This flag is cleared by the appropriate ed
ge
detection of the Display Vertical Blank signal assertion.
2
DISPLAY FLIP PENDING: If this bit is set, and this instruction is executed out of a
Batch Buffer, the Parser halts when it parses this instruction until the flip event (new
front buffer address has now been loaded into the active front buffer registers) . If
executed out of a ring buffer, the Parser sets a flag that eliminates that ring from the
arbitration till the flip event. If there is no flip pending, the parser just proceeds.
Batch Buffer, the Parser halts when it parses this instruction until the flip event (new
front buffer address has now been loaded into the active front buffer registers) . If
executed out of a ring buffer, the Parser sets a flag that eliminates that ring from the
arbitration till the flip event. If there is no flip pending, the parser just proceeds.
Mechanism: The execution of a front buffer packet by the parser sets a flag
(FlipPendingFlag) that is cleared by the flip event. If the FlipPendingFlag is set and this
instruction shows up with this bit set, then the parser will wait for flip event just as
described for the bit above. If FlipPendingFlag is not set and this instructions shows up
with this bit set, the instruction has no effect and parser moves on. If the execution of
this instruction happens to coincide with the flip event, the parser behaves as if the
FlipPendingFlag is not set. The flip event can be a function of hsync or vsync as
selected by the front buffer packet.
(FlipPendingFlag) that is cleared by the flip event. If the FlipPendingFlag is set and this
instruction shows up with this bit set, then the parser will wait for flip event just as
described for the bit above. If FlipPendingFlag is not set and this instructions shows up
with this bit set, the instruction has no effect and parser moves on. If the execution of
this instruction happens to coincide with the flip event, the parser behaves as if the
FlipPendingFlag is not set. The flip event can be a function of hsync or vsync as
selected by the front buffer packet.
1
SCAN LINES: This instruction with this bit set should be sent after the
LOAD_SCAN_LINES instruction. If executed out of a batch buffer, this instruction will
cause the parser to halt and wait if the scan_line_window indicator is asserted. If the
scan line window indicator is de-asserted, the parser just moves on. If executed out of a
ring buffer, the Parser sets a flag if the scan line window indicator is asserted. This flag
eliminates that ring from the arbitration until the it is cleared. This flag is cleared by the
trailing edge of the scan_line_window indicator. If the scan line window indicator is
deasserted the flag is not set and the parser moves on. For more information look at the
load_scan_line packet.
LOAD_SCAN_LINES instruction. If executed out of a batch buffer, this instruction will
cause the parser to halt and wait if the scan_line_window indicator is asserted. If the
scan line window indicator is de-asserted, the parser just moves on. If executed out of a
ring buffer, the Parser sets a flag if the scan line window indicator is asserted. This flag
eliminates that ring from the arbitration until the it is cleared. This flag is cleared by the
trailing edge of the scan_line_window indicator. If the scan line window indicator is
deasserted the flag is not set and the parser moves on. For more information look at the
load_scan_line packet.
0
Reserved: 0