Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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2.2.6. System
Clocking
The Intel
®
82815 chipset GMCH has a new type of clocking architecture. It has integrated SDRAM
buffers that run at either 100 or 133 MHz, independent of the system bus frequency. See table below for
supported system bus and system memory bus frequencies. The system bus frequency is selectable
between 66 MHz, 100 MHz or 133 MHz. The GMCH uses a copy of the USB clock as the DOT Clock
input for the graphics pixel clock PLL.
supported system bus and system memory bus frequencies. The system bus frequency is selectable
between 66 MHz, 100 MHz or 133 MHz. The GMCH uses a copy of the USB clock as the DOT Clock
input for the graphics pixel clock PLL.
Table 1.
Supported System Bus and System Memory Bus Frequencies
Front Side Bus
Frequency
System Memory
Bus Frequency
Display Cache Interface
Frequency
66 MHz
100 MHz
133 MHz or DVMT
100 MHz
100 MHz
133 MHz or DVMT
133 MHz
100 MHz
133 MHz or DVMT
133 MHz
133 MHz
133 MHz or DVMT
2.2.7.
GMCH Power Delivery
The Intel
®
82815 chipset GMCH core voltage is 1.85V. System Memory runs off of a 3.3V supply.
Display cache memory runs off of the AGP 3.3V supply. AGP 1X/2X I/O can run off of either a 3.3V or
a 1.5V supply. AGP 4X I/O require a 1.5V supply. The AGP interface voltage is determined by the
VDDQ generation on the motherboard.
a 1.5V supply. AGP 4X I/O require a 1.5V supply. The AGP interface voltage is determined by the
VDDQ generation on the motherboard.
2.3.
Three PCI Devices on GMCH
The Intel
®
82815 chipset GMCH contains three PCI Devices. The management of active devices is
controlled via bit 0 of the APCONT register (See the Intel
®
815 Chipset: 82815 Graphics and Memory
Controller (GMCH) EDS for details on PCI configuration registers).
• Device 0 = Host Bridge = PCI bus #0 interface, Main Memory Controller, Graphics Aperture
controller
• Device 1 = AGP Bridge = AGP 2X/4X interface (AGP Mode)
• Device 2 = Internal Graphics Device (GFX Mode)
• Device 2 = Internal Graphics Device (GFX Mode)
Note: Devices 1 and 2 are mutually exclusive. Only one of these two devices can be active at any given time.
Device selection is performed during the start-up sequence and can only be set once. The lock bit must
be set after device selection.
be set after device selection.
The following diagram shows more detail at a platform level. The GMCH is shown in both AGP Mode
(left side) and GFX Mode (right side). Only one mode can be active at any given time. The processor and
ICH functions remain unchanged by the GMCH mode of operation.
(left side) and GFX Mode (right side). Only one mode can be active at any given time. The processor and
ICH functions remain unchanged by the GMCH mode of operation.