Intel 815 Manuel D’Utilisation

258  

 

1.  Write the Display Clock 2 Divisor register with the M-REG value and N-REG value. 
2.  Write the clock 2 byte of the Display & LCD Clock Divisor Select Register with the P-REG value. 
3.  Write the MSR register, bit 3 = '1', to select DCLK2. 

1.  Write the LCD clock Divisor register with the M-REG value and N-REG value. 
2.  Write the LCD byte of the Display & LCD Clock divisor Select Register with the P-REG value. 
3.  Write the LCD / TV-Out Control[31] = 1 and [0] = 1; MSR[3:2] are ignored when this condition is 

true. 

Address Offset: 

06000h–06003h 

Default Value: 

00030013h 

Attribute: R/W 
Size: 32 

bits 

The Display Clock 0 Divisor register and the Display & LCD Clock Divisor Select Register are 
programmed with the loop parameters to be loaded into the clock synthesizer.  

Data is written to the Display Clock 0 Divisor register followed by a write to the Clock 0 byte of the 
Display & LCD Clock Divisor Select Register. The completion of the write to the Display & LCD 
Clock Divisor Select Register causes data from both registers to transfer to the VCO register file simul-
taneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock 
programming sequence. 

 

31 26 

25 16 

15 10 

9  0 

Reserved 

VCO 0 N-Divisor 

Reserved 

VCO 0 M-Divisor 

 

31:26 

Reserved.  

25:16 

VCO 0 N-Divisor. N-Divisor value calculated for the desired output frequency. (default = 03h) 

15:10 

Reserved. 

9:0 

VCO 0 M-Divisor. M-Divisor value calculated for the desired output frequency. (default = 13h)