Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
259
14.3.
DCLK_1D—Display Clock 1 Divisor Register
Address Offset:
06004h–06007h
Default Value:
00100053h
Attribute: R/W
Size: 32
Size: 32
bits
The Display Clock 1 Divisor register and the Display & LCD Clock Divisor Select Register are
programmed with the loop parameters to be loaded into the clock synthesizer.
programmed with the loop parameters to be loaded into the clock synthesizer.
Data is written to the Display Clock 1 Divisor register followed by a write to the Clock 1 byte of the
Display & LCD Clock Divisor Select Register. The completion of the write to the Display & LCD
Clock Divisor Select Register causes data from both registers to transfer to the VCO register file simul-
taneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock
programming sequence.
Display & LCD Clock Divisor Select Register. The completion of the write to the Display & LCD
Clock Divisor Select Register causes data from both registers to transfer to the VCO register file simul-
taneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock
programming sequence.
31 26
25 16
15 10
9 0
Reserved
VCO 1 N-Divisor
Reserved
VCO 1 M-Divisor
Bit Description
31:26
Reserved
25:16
VCO 1 N-Divisor. N-Divisor value calculated for the desired output frequency. (default = 10h)
15:10
Reserved
9:0
VCO 1 M-Divisor. M-Divisor value calculated for the desired output frequency. (default = 53h)