Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
267
15.1.
OV0ADD—Overlay 0 Register Update Address Register
Memory Address Offset:
30000h–30003h
Default Value:
00000000
Access: R/W
Size:
Size:
32 bits
This register provides a physical memory address that will be used on the next register update for
Overlay 0. This register is double buffered to allow it to be updated during overlay display.
Overlay 0. This register is double buffered to allow it to be updated during overlay display.
Updating Register Values
A write to this register sets an internal bit (readable through the status register) that causes all the register
values that were written to the memory buffer area to be loaded into the corresponding on-chip registers
and become active on the next VBLANK event. Overlay 0 Flip is asserted after all registers are updated
from memory.
values that were written to the memory buffer area to be loaded into the corresponding on-chip registers
and become active on the next VBLANK event. Overlay 0 Flip is asserted after all registers are updated
from memory.
Debug Read Path For Overlay 0 Registers
The read path is the active register. The staging register is not readable.
Memory Address Offset:
30100h–301xxh (xx=register offset)
These registers will provide a debug read path for testing overlay internal register functionality. The
address offsets correspond to the memory offsets used to load the registers.
address offsets correspond to the memory offsets used to load the registers.
31 29
28
0
Reserved Register
Update
Address
Bit Description
31:29
Reserved.
28:0
Register Update Address. Physical memory address that will be used on the next register update for
Overlay 0..
Overlay 0..