Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
269
Bit Description
20:19
Overlay 0 Current Buffer/Field. This field indicates the Current Buffer. Updated at display VBLANK
before the interrupt, this field is only valid when in field (interlaced) mode.
before the interrupt, this field is only valid when in field (interlaced) mode.
00 = Buffer 0 Field 0
01 = Buffer 0 Field 1
10 = Buffer 1 Field 0
11 = Buffer 1 Field 1
18:15
Reserved.
14
Not Active Pixel. This bit indicates the Display Horizontal Blank Active state (includes Border).
Updated real time, set by leading edge of Overlay’s display HBLANK and cleared by the trailing edge
of Overlay’s HBLANK.
Updated real time, set by leading edge of Overlay’s display HBLANK and cleared by the trailing edge
of Overlay’s HBLANK.
0 = HBlank inactive
1 = HBlank active (default).
13
Reserved.
12
Not Active Video Scan Line. This bit indicates the Display Vertical Blank Active state (includes
Border). Updated real time, set by leading edge of Overlay’s display VBLANK and cleared by the
trailing edge of Overlay’s VBLANK.
Border). Updated real time, set by leading edge of Overlay’s display VBLANK and cleared by the
trailing edge of Overlay’s VBLANK.
0 = VBlank inactive
1 = VBlank active (default).
11
Reserved.
10:0
Display Line Status. This field displays the line number. Reset to zero at the trailing edge of display
VBLANK. Incremented at the trailing edge of Overlay’s display HBLANK
VBLANK. Incremented at the trailing edge of Overlay’s display HBLANK
15.3. Gamma
Correction
Note that the registers in this section are read from or written to directly at the memory address offset
location specified.
location specified.
15.3.1.1.
GAMC[5:0]—Gamma Correction Registers
Memory Address Offset:
30010h–30027h
GAMC5 = 30010h
GAMC4 = 30014h
GAMC3 = 30018h
GAMC2 = 3001Ch
GAMC1 = 30020h
GAMC0 = 30024h
Default Value:
GAMC5 = C0C0C0h
GAMC4 = 808080h
GAMC3 = 404040h
GAMC2 = 202020h
GAMC1 = 101010h
GAMC0 = 080808h
Access: R/W
Size:
Size:
32 bits