Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
324
16.2.3. IIR—Interrupt Identity Register
Address Offset:
020A4h
Default Value:
0000h
Access: Read/Write
Clear
Size: 16
bits
The individual interrupt(s), which occurred, are determined via this register. The bit is set by the
interrupt event and held until cleared by writing a ‘1’ into the bit position.
interrupt event and held until cleared by writing a ‘1’ into the bit position.
15 14
13 12
11
10
9
8
HW
Detect
Error
Master
Reserved Sync
Status
Toggle
Pri Dply
Flip
Pending
Reserved Overlay
0
Flip
Pending
Reserved
7 6 5 4 3 2 1 0
Pri Dply
VBLANK.
Pri Dply
Event
Reserved Reserved Reserved Reserved User
Defined
Interrupt
Breakpoint
Bit Description
15:0
Interrupt Identity. See. Table 17
1 = Interrupt occurred.