Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
357
Bit Descriptions
0
GUI Mode.
0 = Standard VGA and extended 4 bpp/16 color resolutions (default). Can still access memory in linear
mode.
1 = High Resolution (i.e., not VGA or extended planar).
Transition from VGA modes to hires mode or opposite:
Software will turn the display engine off (screen off) using SR01[Screen Off] and wait for at least two
HSYNC periods and no more than two VSYNC periods (since one of the isochronous streams is
DRAM refresh (controlled by DRAMCXH[DRAM Refresh Status]), the wait should not be so long as to
cause the DRAM content to degrade) before writing to PIXCONF[0] and turning the display on. This
should ensure that all the data requested from the display engine will be out of the local memory
interface before PIXCONF is touched. In addition, while switching from hi-res to VGA or VGA to hi-res,
software will ensure that all the other isochronous streams are off before programming PIXCONF[0].
Software will turn the display engine off (screen off) using SR01[Screen Off] and wait for at least two
HSYNC periods and no more than two VSYNC periods (since one of the isochronous streams is
DRAM refresh (controlled by DRAMCXH[DRAM Refresh Status]), the wait should not be so long as to
cause the DRAM content to degrade) before writing to PIXCONF[0] and turning the display on. This
should ensure that all the data requested from the display engine will be out of the local memory
interface before PIXCONF is touched. In addition, while switching from hi-res to VGA or VGA to hi-res,
software will ensure that all the other isochronous streams are off before programming PIXCONF[0].
NOTES:
Bits [27:24] are not normally used by the graphics BIOS or by the drivers because the gamma values are
specific to a particular display device, and apply to two color or hi-color modes (16 and 24 bit). It is
necessary to program the palette first with the gamma adjusted values. There is only one palette, so if
both 3:2 are set, they have the same gamma adjustments. Typical code and typical drivers leave these
bits as zero.
specific to a particular display device, and apply to two color or hi-color modes (16 and 24 bit). It is
necessary to program the palette first with the gamma adjusted values. There is only one palette, so if
both 3:2 are set, they have the same gamma adjustments. Typical code and typical drivers leave these
bits as zero.
20.3.2. BLTCNTL—BLT
Control
Memory Offset Address:
7000Ch
Default: 0000h
Attributes: Read/Write
Attributes: Read/Write
15
1
0
Reserved BLT
Status
Bit Descriptions
15:1
Reserved.
0
BLT Status – RO. This read-only bit reflects the busy status of BLT Engine only.
0 = Idle (default)
1 = Busy
20.3.3. SWF[1:3]—Software Flag Registers
Memory Offset Address:
SWF1 =70014h
SWF2 = 70018h
SWF3 = 7001Ch
Default: 00000000h
Attributes: Read/Write
Attributes: Read/Write
These 32-bit registers are used as scratch pad space in BIOS, and have no effect on hardware.