Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
358
20.3.4. DPLYBASE—Display Base Address Register
Memory Offset Address:
70020h
Default: 0000h
Attributes: Read/Write
Attributes: Read/Write
The display can be read from graphics memory. This register is the display staging register when written.
The load register is transferred into the active register on the asserting edge of Vertical Sync. The read
back register is from the active register.
The load register is transferred into the active register on the asserting edge of Vertical Sync. The read
back register is from the active register.
31
26
25
3
2
0
Reserved
Display Base Address Bits
Reserved
Bit Descriptions
31:26
Reserved. Bits <27:26> are implemented as scratch bits.
25:3
Display Base Address Bits [25:03]. This is the base address of the display.
2:0
Reserved.