Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
91
9.3.2. GR00
Set/Reset Register
I/O (and Memory Offset) Address: 3CFh (index=00h)
Default: 0Uh
Default: 0Uh
(U=Undefined)
Attributes: Read/Write
7
4
3 2 1 0
Reserved (0000)
Set/Reset
Plane 3
Set/Reset
Plane 2
Set/Reset
Plane 1
Set/Reset
Plane 0
Bit Description
7:4
Reserved. Read as 0s.
3:0
Set/Reset Plane [3:0]. When the Write Mode bits (bits 0 and 1) of the Graphics Mode Register (GR05)
are set to select Write Mode 0, all 8 bits of each byte of each memory plane are set to either 1 or 0 as
specified in the corresponding bit in this register, if the corresponding bit in the Enable Set/Reset
Register (GR01) is set to 1.
are set to select Write Mode 0, all 8 bits of each byte of each memory plane are set to either 1 or 0 as
specified in the corresponding bit in this register, if the corresponding bit in the Enable Set/Reset
Register (GR01) is set to 1.
When the Write Mode bits (bits 0 and 1) of the Graphics Mode Register (GR05) are set to select Write
Mode 3, all processor data written to the frame buffer is rotated, then logically ANDed with the contents
of the Bit Mask Register (GR08), and then treated as the addressed data’s bit mask, while value of
these four bits of this register are treated as the color value.
Mode 3, all processor data written to the frame buffer is rotated, then logically ANDed with the contents
of the Bit Mask Register (GR08), and then treated as the addressed data’s bit mask, while value of
these four bits of this register are treated as the color value.
9.3.3. GR01
Enable Set/Reset Register
I/O (and Memory Offset) Address: 3CFh (Index=01h)
Default: 0Uh
Default: 0Uh
(U=Undefined)
Attributes: Read/Write
7
4
3 2 1 0
Reserved (0000)
Enable
Set/
Reset Pln
3
Enable
Set/ Reset
Pln
2
Enable
Set/
Reset Pln
1
Enable
Set/ Reset
Pln
0
Bit Description
7:4
Reserved. Read as 0s.
3:0
Enable Set/Reset Plane [3:0]. This register works in conjunction with the Set/Reset Register (GR00).
The Write Mode bits (bits 0 and 1) must be set for Write Mode 0 for this register to have any effect.
The Write Mode bits (bits 0 and 1) must be set for Write Mode 0 for this register to have any effect.
0 = The corresponding memory plane can be read from or written to by the processor without any
special bitwise operations taking place.
1 = The corresponding memory plane is set to 0 or 1 as specified in the Set/Reset Register (GR00).