Intel 253666-024US Manuel D’Utilisation
3-488 Vol. 2A
INVLPG—Invalidate TLB Entry
INSTRUCTION SET REFERENCE, A-M
INVLPG—Invalidate TLB Entry
Description
Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the
source operand. The source operand is a memory address. The processor determines
the page that contains that address and flushes the TLB entry for that page.
The INVLPG instruction is a privileged instruction. When the processor is running in
protected mode, the CPL of a program or procedure must be 0 to execute this
instruction.
The INVLPG instruction normally flushes the TLB entry only for the specified page;
however, in some cases, it flushes the entire TLB. See “MOV—Move to/from Control
Registers” in this chapter for further information on operations that flush the TLB.
This instruction’s operation is the same in all non-64-bit modes. It also operates the
same in 64-bit mode, except if the memory address is in non-canonical form. In this
case, INVLPG is the same as a NOP.
source operand. The source operand is a memory address. The processor determines
the page that contains that address and flushes the TLB entry for that page.
The INVLPG instruction is a privileged instruction. When the processor is running in
protected mode, the CPL of a program or procedure must be 0 to execute this
instruction.
The INVLPG instruction normally flushes the TLB entry only for the specified page;
however, in some cases, it flushes the entire TLB. See “MOV—Move to/from Control
Registers” in this chapter for further information on operations that flush the TLB.
This instruction’s operation is the same in all non-64-bit modes. It also operates the
same in 64-bit mode, except if the memory address is in non-canonical form. In this
case, INVLPG is the same as a NOP.
IA-32 Architecture Compatibility
The INVLPG instruction is implementation dependent, and its function may be imple-
mented differently on different families of Intel 64 or IA-32 processors. This instruc-
tion is not supported on IA-32 processors earlier than the Intel486 processor.
mented differently on different families of Intel 64 or IA-32 processors. This instruc-
tion is not supported on IA-32 processors earlier than the Intel486 processor.
Operation
Flush(RelevantTLBEntries);
Continue; (* Continue execution *)
Continue; (* Continue execution *)
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
Operand is a register.
If the LOCK prefix is used.
If the LOCK prefix is used.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01/7
INVLPG m
Valid
Valid
Invalidate TLB Entry for page that
contains m.
NOTES:
* See the IA-32 Architecture Compatibility section below.