jetway i407r1a Manuel D’Utilisation
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3-6 Advanced Chipset Features
The Advanced Chipset Features Setup option is used to change the values of the chipset
registers. These registers control most of the system options in the computer.
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Advanced Chipset Features
Item Help
> DRAM Timing Settings Press Enter
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
Memory Hole At 15M-16M Disabled
Delay Transaction Enabled
AGP Aperture Size 64MB
Delay Prior Thermal 16 Min
Menu Level >
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
DRAM Timing Settings
Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.