jetway i407r1a Manuel D’Utilisation
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3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
DRAM Timing Settings
Item Help
Auto Configuration Standard
SDRAM CAS Latency Time 2.5
SDRAM Cycle Time 6
SDRAM RAS# to CAS# Delay 3
SDRAM RAS# Precharge 3
Menu Level >>
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
SDRAM RAS# To CAS# Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T (Default).
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T (Default).
SDRAM RAS# Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T (Default).
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T (Default).
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 1.5T, 2T and 2.5T (Default).
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 1.5T, 2T and 2.5T (Default).
Note: Change these settings only if you are familiar with the chipset.
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Integrated Peripherals
Item Help
> Onboard IDE Function Press Enter
> Onboard Device Function Press Enter
> Onboard Super IO Function Press Enter
Init Display First PCI Slot
Power On Function Button Only
KB Power On Password Enter
Hot Key Power On Ctrl-F1
Power After Power Fail Always Off
Menu Level >
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults