jetway v333ur1a Manuel D’Utilisation

 
 
 
                                                                                                                                                                                                                                                                                                                                                         

 
 
 

 

RAS Precharge Time 
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before 
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.  Fast 
gives faster performance; and Slow gives more stable performance.  This field applies only 
when synchronous DRAM is installed in the system.  The settings are: 2T and 3T. 
CAS Latency 
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends 
on the DRAM timing.  The settings are: 2T and 2.5T. 
 
 

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PCI Delay Transaction 
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.  
Select Enabled to support compliance with PCI specification version 2.1.  The settings are: 
Enabled and Disabled.