Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
Programmer’s Model
2-26
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
Figure 2-11 Register c8 MVA format
Note
If either small or large pages are used, and these pages contain subpage access
permissions that are different, then you must use four invalidate TLB single entry
operations, with the MVA set to each subpage, to invalidate all information related to
that page held in a TLB.
permissions that are different, then you must use four invalidate TLB single entry
operations, with the MVA set to each subpage, to invalidate all information related to
that page held in a TLB.
2.3.10
Cache Lockdown and TCM Region Registers c9
Register c9 accesses the Cache Lockdown and TCM Region Registers. The register
accessed is determined by the value of the CRm field:
accessed is determined by the value of the CRm field:
CRm = c0 selects the Cache Lockdown Register
CRm = c1 selects the TCM Region Register.
Other values of CRm are reserved.
Cache Lockdown Register c9
The Cache Lockdown Register uses a cache-way-based locking scheme (Format C) that
enables you to control each cache way independently.
enables you to control each cache way independently.
These registers enable you to control which cache ways of the four-way cache are used
for the allocation on a linefill. When the registers are defined, subsequent linefills are
only placed in the specified target cache way. This gives you some control over the
cache pollution caused by particular applications, and provides a traditional lockdown
operation for locking critical code into the cache.
for the allocation on a linefill. When the registers are defined, subsequent linefills are
only placed in the specified target cache way. This gives you some control over the
cache pollution caused by particular applications, and provides a traditional lockdown
operation for locking critical code into the cache.
A locking bit for each cache way determines if the normal cache allocation is allowed
to access that cache way. See Table 2-21 on page 2-28.
to access that cache way. See Table 2-21 on page 2-28.
A maximum of three cache ways of the four-way associative cache can be locked,
ensuring that normal cache line replacement is performed.
ensuring that normal cache line replacement is performed.
Note
If no cache ways have L bits set to 0, then cache way 3 is used for all linefills.
Modified virtual address
31
10 9
0
SBZ