Manuels d'utilisation pour Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK

Atmel

Codes de produits

AT91SAM9N12-EK

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Fiche De Données (AT91SAM9N12-EK)

Table des matières

Contents
3
List of Tables
7
List of Figures
11
Preface
15
- About this manual
  16
  - Product revision status
    16
  - Intended audience
    16
  - Using this manual
    16
  - Conventions
    18
  - Further reading
    20
- Feedback
  21
  - Feedback on the product
    21
  - Feedback on this manual
    21
Introduction
23
- 1.1 About the ARM926EJ-S processor
  24
Programmer’s Model
29
- 2.1 About the programmer’s model
  30
- 2.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers
  31
  - 2.2.1 Addresses in an ARM926EJ-S system
    32
  - 2.2.2 Accessing CP15 registers
    32
- 2.3 Register descriptions
  35
Memory Management Unit
65
- 3.1 About the MMU
  66
- 3.2 Address translation
  69
- 3.3 MMU faults and CPU aborts
  85
  - 3.3.1 Fault address and fault status registers
    85
- 3.4 Domain access control
  88
- 3.5 Fault checking sequence
  90
- 3.6 External aborts
  93
  - 3.6.1 Enabling the MMU
    93
  - 3.6.2 Disabling the MMU
    94
- 3.7 TLB structure
  95
Caches and Write Buffer
97
- 4.1 About the caches and write buffer
  98
- 4.2 Write buffer
  100
- 4.3 Enabling the caches
  101
- 4.4 TCM and cache access priorities
  104
- 4.5 Cache MVA and Set/Way formats
  105
Tightly-Coupled Memory Interface
109
- 5.1 About the tightly-coupled memory interface
  110
- 5.2 TCM interface signals
  112
- 5.3 TCM interface bus cycle types and timing
  116
- 5.4 TCM programmer’s model
  127
  - 5.4.1 Enabling the ITCM
    127
  - 5.4.2 Enabling the DTCM
    127
  - 5.4.3 Disabling the ITCM
    127
  - 5.4.4 Disabling the DTCM
    127
  - 5.4.5 Cachable and bufferable attributes
    127
- 5.5 TCM interface examples
  128
- 5.6 TCM access penalties
  137
- 5.7 TCM write buffer
  138
- 5.8 Using synchronous SRAM as TCM memory
  139
- 5.9 TCM clock gating
  140
Bus Interface Unit
141
- 6.1 About the bus interface unit
  142
- 6.2 Supported AHB transfers
  143
Noncachable Instruction Fetches
153
- 7.1 About noncachable instruction fetches
  154
  - 7.1.1 Uses of noncachable code
    154
  - 7.1.2 Self modifying code
    154
  - 7.1.3 AHB behavior
    155
Coprocessor Interface
157
- 8.1 About the ARM926EJ-S external coprocessor interface
  158
  - 8.1.1 Overview
    158
- 8.2 LDC/STC
  160
- 8.3 MCR/MRC
  162
  - 8.3.1 Interlocked MCR
    163
- 8.4 CDP
  164
- 8.5 Privileged instructions
  165
- 8.6 Busy-waiting and interrupts
  166
- 8.7 CPBURST
  167
- 8.8 CPABORT
  168
- 8.9 nCPINSTRVALID
  169
- 8.10 Connecting multiple external coprocessors
  170
Instruction Memory Barrier
171
- 9.1 About the instruction memory barrier operation
  172
- 9.2 IMB operation
  173
- 9.3 Example IMB sequences
  175
Embedded Trace Macrocell Support
177
- 10.1 About Embedded Trace Macrocell support
  178
  - 10.1.1 FIFOFULL
    178
Debug Support
181
- 11.1 About debug support
  182
  - 11.1.1 Debug clocks
    182
  - 11.1.2 Scan chain 15
    182
Power Management
185
- 12.1 About power management
  186
  - 12.1.1 Dynamic power management (wait for interrupt mode)
    186
  - 12.1.2 Static power management (leakage control)
    187
Signal Descriptions
189
- A.1 Signal properties and requirements
  190
- A.2 AHB related signals
  191
- A.3 Coprocessor interface signals
  193
- A.4 Debug signals
  195
- A.5 JTAG signals
  197
- A.6 Miscellaneous signals
  198
- A.7 ETM interface signals
  200
- A.8 TCM interface signals
  202
CP15 Test and Debug Registers
207
- B.1 About the Test and Debug Registers
  208
Glossary
225
Index
245
- A
  245
- B
  245
- C
  245
- D
  246
- E
  246
- F
  246
- H
  246
- I
  246
- J
  246
- L
  246
- M
  247
- N
  247
- O
  247
- P
  247
- R
  247
- S
  247
- T
  248
- U
  248
- V
  248
- W
  248
- Z
  248

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Table des matières

Section 1
5
- Introduction
  5
Section 2
6
- Kit Contents
  6
Section 3
8
- Power Up
  8
Section 4 3
9
- Evaluation Kit Hardware
  9
  - 4.1 Board Overview
    9
  - 4.2 Equipment List
    10
  - 4.3 Function Blocks
    13
    - 4.3.1 Processor
      13
    - 4.3.2 Clock Distribution
      13
    - 4.3.3 Reset and Wake-up Circuitry
      14
    - 4.3.4 Power Supplies
      14
    - 4.3.5 Power Rails
      15
    - 4.3.6 Battery Backup
      16
    - 4.3.7 Memory
      17
    - 4.3.8 UART DBGU
      18
    - 4.3.9 JTAG Interface
      18
    - 4.3.10 Serial Peripheral Interface (SPI) Controller
      19
    - 4.3.11 Two Wire Interface (TWI)
      19
    - 4.3.12 USB Ports
      20
    - 4.3.13 1-Wire EEPROM
      21
    - 4.3.14 ETH on EBI
      21
    - 4.3.15 Audio
      22
    - 4.3.16 SD Card
      23
    - 4.3.17 ZigBee Interface
      23
    - 4.3.18 Analog Interface
      24
    - 4.3.19 LED Indicators
      24
    - 4.3.20 Push Buttons
      25
    - 4.3.21 Expansion Ports
      26
    - 4.3.22 PIO Usage
      27
  - 4.4 Connectors
    31
    - 4.4.1 Power Supply
      31
    - 4.4.2 JTAG/ICE Connector
      31
    - 4.4.3 DBGU
      32
    - 4.4.4 USB MicroB
      33
    - 4.4.5 USB Type A port
      33
    - 4.4.6 SD Card MCI
      34
    - 4.4.7 Ethernet RJ45 Socket
      35
    - 4.4.8 Zigbee Socket J12
      35
    - 4.4.9 LCD Socket
      36
    - 4.4.10 IO Expansion Port
      38
Section 5
41
- EK Schematics
  41
  - 5.1 SAM9N12-EK Schematics
    41
  - 5.2 SAM9CN11-EK Schematics
    51
Section 6
61
- Display Module Hardware
  61
  - 6.1 Board Overview
    61
  - 6.2 Equipment List
    61
  - 6.3 Function Blocks
    62
    - 6.3.1 3.3V Regulator
      62
    - 6.3.2 TFT LCD with Touch Panel
      62
    - 6.3.3 Back Light
      63
    - 6.3.4 QTouch
      64
    - 6.3.5 1-Wire
      64
Section 7
65
- DM Schematics
  65
  - 7.1 DM Board Schematics
    65
Section 8
67
- Revision History
  67
  - 8.1 Revision History
    67

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