Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données

Atmel

Codes de produits

AT91SAM9N12-EK

ARM DDI0198D

Copyright © 2001-2003 ARM Limited. All rights reserved.

vii

List of Tables
ARM926EJ-S Technical Reference Manual

Change history .............................................................................................................. ii

CP15 register summary ............................................................................................ 2-3

Address types in ARM926EJ-S ................................................................................. 2-4

CP15 abbreviations ................................................................................................... 2-5

Reading from register c0 ........................................................................................... 2-7

Register 0, ID code ................................................................................................... 2-8

Ctype encoding ......................................................................................................... 2-9

Cache size encoding (M=0) .................................................................................... 2-10

Cache associativity encoding (M=0) ....................................................................... 2-10

Line length encoding ............................................................................................... 2-11

Example Cache Type Register format .................................................................... 2-11

Control bit functions register c1 ............................................................................... 2-13

Effects of Control Register on caches ..................................................................... 2-15

Effects of Control Register on TCM interface .......................................................... 2-16

Domain access control defines ............................................................................... 2-18

FSR bit field descriptions ........................................................................................ 2-19

FSR status field encoding ....................................................................................... 2-20

Function descriptions register c7 ............................................................................ 2-21

Cache operations c7 ............................................................................................... 2-22

Register c8 TLB operations ..................................................................................... 2-25

Cache Lockdown Register instructions ................................................................... 2-27

Cache Lockdown Register L bits ............................................................................. 2-28

TCM Region Register instructions .......................................................................... 2-29