Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
1056
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
The T
SLCK
min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz).
T
RES
= 30 µs
T1 = 66 µs
T2 = 352 µs
VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled into the ROM code.
As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to ensure a reliable
operation of the device.
operation of the device.
48.13 SMC Timings
48.13.1 Timing Conditions
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables, t
CPMCK
is MCK period.
48.13.2 Timing Extraction
48.13.2.1 Zero Hold Mode Restrictions
Table 48-24. Capacitance Load
Corner
Supply
MAX
MIN
3.3V
50 pF
5 pF
1.8V
30 pF
5 pF
Table 48-25. Zero Hold Mode Use Maximum system clock frequency (MCK)
Symbol
Parameter
Min
Units
VDDIOM supply
1.8V
3.3V
Zero Hold Mode Use
Fmax
MCK frequency
66
66
MHz