Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
504
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.14 DMAC Channel x [x = 0..7] Destination Address Register
Name:
DMAC_DADDRx [x = 0..7]
Addresses:
0xFFFFEC40 [0], 0xFFFFEC68 [1], 0xFFFFEC90 [2], 0xFFFFECB8 [3], 0xFFFFECE0 [4], 0xFFFFED08 [5],
0xFFFFED30 [6], 0xFFFFED58 [7]
0xFFFFED30 [6], 0xFFFFED58 [7]
Access:
Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in
• DADDR: Channel x Destination Address
This register must be aligned with the destination transfer width.
31
30
29
28
27
26
25
24
DADDR
23
22
21
20
19
18
17
16
DADDR
15
14
13
12
11
10
9
8
DADDR
7
6
5
4
3
2
1
0
DADDR