Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données

510

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Name: 

DMAC_CFGx [x = 0..7]

0xFFFFEC50 [0], 0xFFFFEC78 [1], 0xFFFFECA0 [2], 0xFFFFECC8 [3], 0xFFFFECF0 [4], 0xFFFFED18 [5], 
0xFFFFED40 [6], 0xFFFFED68 [7]

Read-write

0x0100000000

This register can only be written if the WPEN bit is cleared in 

Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.

Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.

0 (CONTIGUOUS_ADDR): When automatic mode is activated, source address is contiguous between two buffers.

1 (RELOAD_ADDR): When automatic mode is activated, the source address and the control register are reloaded from previous 
transfer.

0 (SW): Software handshaking interface is used to trigger a transfer request.

1 (HW): Hardware handshaking interface is used to trigger a transfer request.

This field indicates the Most Significant bits of the SRC_PER field.

0 (CONTIGUOUS_ADDR): When automatic mode is activated, destination address is contiguous between two buffers.

1 (RELOAD_ADDR): When automatic mode is activated, the destination and the control register are reloaded from the previous 
transfer.

0 (SW): Software handshaking interface is used to trigger a transfer request.

1 (HW): Hardware handshaking interface is used to trigger a transfer request.

31

30

29

28

27

26

25

24

–

–

FIFOCFG

–

AHB_PROT

23

22

21

20

19

18

17

16

–

LOCK_IF_L

LOCK_B

LOCK_IF

–

–

–

SOD

15

14

13

12

11

10

9

8

DST_PER_MSB

DST_H2SEL

DST_REP

SRC_PER_MSB

SRC_H2SEL

SRC_REP

7

6

5

4

3

2

1

0

DST_PER

SRC_PER