Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données

Codes de produits

AT91SAM9N12-EK

847

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

41.5.2.3 Receiver Ready

When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read.

Figure 41-5. Receiver Ready

41.5.2.4 Receiver Overrun

If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last
transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is
cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1.

Figure 41-6. Receiver Overrun

41.5.2.5 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in UART_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
UART_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register UART_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.

Figure 41-7. Parity Error

URXD

Read UART_RHR

RXRDY

URXD

RSTSTA

RXRDY

OVRE

stop

URXD

RSTSTA

RXRDY

PARE

Wrong Parity Bit