Intel E3815 FH8065301567411 Fiche De Données

Codes de produits

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

Datasheet

Table 190

SATA/AHCI Feature Matrix....................................................................1921

Table 191

Summary of SATA PCI Configuration Registers—0/19/0............................1924

Table 192

Summary of SATA Legacy I/O Registers—LBAR .......................................1953

Table 193

Summary of SATA Index Pair I/O Registers—ABAR ..................................1959

Table 194

Summary of SATA AHCI Memory Mapped I/O Registers—ABAR..................1961

Table 195

Summary of SATA Primary Read Command I/O Registers—PCMDIDEBA......1998

Table 196

Summary of SATA Primary Write Command I/O Registers—PCMDIDEBA .....2003

Table 197

Summary of SATA Primary Read Control I/O Registers—PCTLIDEBA ...........2005

Table 198

Summary of SATA Primary Write Control I/O Registers—PCTLIDEBA ..........2006

Table 199

Summary of SATA Secondary Read Command I/O Registers—SCMDIDEBA..2007

Table 200

Summary of SATA Secondary Write Command I/O Registers—SCMDIDEBA .2012

Table 201

Summary of SATA Secondary Read Control I/O Registers—SCTLIDEBA .......2014

Table 202

Summary of SATA Secondary Write Control I/O Registers—SCTLIDEBA ......2015

Table 203

Summary of SATA Lane 0 Electrical Message Bus Registers—0xA3 (Global Offset

2200h) ..............................................................................................2017

Table 204

Summary of SATA Lane 0 Electrical Message Bus Registers—0xA3 (Global Offset

2280h) ..............................................................................................2047

Table 205

Summary of SATA Lane 1 Electrical Message Bus Registers—0xA3 (Global Offset

2400h) ..............................................................................................2065

Table 206

Summary of SATA Lane 1 Electrical Message Bus Registers—0xA3 (Global Offset

2480h) ..............................................................................................2095

Table 207

USB 3 SS Signals ................................................................................2113

Table 208

USB 2 FS/HS Signals ...........................................................................2113

Table 209

USB 2 HSIC Signals .............................................................................2113

Table 210

Summary of USB xHCI PCI Configuration Registers—0/20/0......................2120

Table 211

Summary of USB xHCI Memory Mapped I/O Registers—MBAR ...................2163

Table 212

Summary of USB EHCI PCI Configuration Registers—0/29/0......................2345

Table 213

Summary of USB EHCI Memory Mapped I/O Registers—MBAR ...................2369

Table 214

Summary of USB EHCI Message Bus Registers—0x43...............................2427

Table 215

USB 3.0 Device Signals ........................................................................2444

Table 216

USB ULPI Device Signals ......................................................................2444

Table 217

Summary of USB 3.0 Device PCI Configuration Registers—0/22/0..............2447

Table 218

Summary of USB 3.0 Device PCI Configuration Registers—0/22/0..............2456

Table 219

Summary of USB 3.0 Device Memory Mapped I/O Registers—BAR .............2461

Table 220

Summary of USB 3.0 Device Memory Mapped I/O Registers—BAR .............2642

Table 221

Signals ..............................................................................................2663

Table 222

Summary of HD Audio PCI Configuration Registers—0/27/0 ......................2667

Table 223

Summary of HD Audio Memory Mapped I/O Registers—AZLBAR.................2698

Table 224

LPE Signals.........................................................................................2799

Table 225

Clock Frequencies ...............................................................................2805

Table 226

M/N Values, Examples .........................................................................2807

Table 227

M/N Configurable Fields .......................................................................2808

Table 228

Programmable Protocol Parameters .......................................................2813

Table 229

Summary of Low Power Audio PCI Configuration Registers—0/21/0............2819

Table 230

Summary of Memory Mapped I/O Registers—0/21/0 ................................2827

Table 231

Summary of LPE Shim Memory Mapped I/O Registers—BAR ......................2837

Table 232

Summary of Low Power Audio I

S0 Memory Mapped I/O Registers—BAR ....2864

Table 233

Summary of Low Power Audio I

S0 Memory Mapped I/O Registers—BAR ....2884

Table 234

Summary of Low Power Audio I

S0 Memory Mapped I/O Registers—BAR ....2904

Table 235

Summary of Low Power Audio DMA0 Memory Mapped I/O Registers—

lpe_bridge.BAR ...................................................................................2924

Table 236

Summary of Low Power Audio DMA1 Memory Mapped I/O Registers—

lpe_bridge.BAR ...................................................................................3037

Table 237

Summary of TXE PCI Configuration Registers—0/26/0..............................3153