Manuels d'utilisation pour LSI 53C875A

Table des matières

• LSI53C875A PCI to Ultra SCSI

  1
• Controller

  1
  • Chapter1 General Description

    15
    • Figure1.1 Typical LSI53C875A System Application

      16
    • Figure1.2 Typical LSI53C875A Board Application

      16
    • 1.1 New Features in the LSI53C875A

      17
    • 1.2 Benefits of Ultra SCSI

      17
    • 1.3 TolerANT® Technology

      18
    • 1.4 LSI53C875A Benefits Summary

      18
      • 1.4.1 SCSI Performance

        19
      • 1.4.2 PCI Performance

        20
      • 1.4.3 Integration

        20
      • 1.4.4 Ease of Use

        20
      • 1.4.5 Flexibility

        21
      • 1.4.6 Reliability

        22
      • 1.4.7 Testability

        22
  • Chapter2 Functional Description

    23
    • Figure2.1 LSI53C875A Block Diagram

      24
    • 2.1 PCI Functional Description

      24
      • 2.1.1 PCI Addressing

        24
      • 2.1.2 PCI Bus Commands and Functions Supported

        25
        • Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C875A

          26
      • 2.1.3 PCI Cache Mode

        31
        • Table 2.2 PCI Cache Mode Alignment

          34
    • 2.2 SCSI Functional Description

      38
      • 2.2.1 SCRIPTS Processor

        39
      • 2.2.2 Internal SCRIPTS RAM

        40
      • 2.2.3 64-Bit Addressing in SCRIPTS

        41
      • 2.2.4 Hardware Control of SCSI Activity LED

        41
      • 2.2.5 Designing an Ultra SCSI System

        42
      • 2.2.6 Prefetching SCRIPTS Instructions

        43
      • 2.2.7 Opcode Fetch Burst Capability

        44
      • 2.2.8 Load and Store Instructions

        44
      • 2.2.9 JTAG Boundary Scan Testing

        45
      • 2.2.10 SCSI Loopback Mode

        45
      • 2.2.11 Parity Options

        46
        • Table 2.3 Bits Used for Parity Control and Generation

          47
        • Table 2.4 SCSI Parity Control

          48
        • Table 2.5 SCSI Parity Errors and Interrupts

          48
        • Figure2.2 Parity Checking/Generation

          49
      • 2.2.12 DMA FIFO

        49
        • Figure2.3 DMA FIFO Sections

          50
        • Figure2.4 LSI53C875A Host Interface SCSI Data Paths

          51
      • 2.2.13 SCSI Bus Interface

        54
        • Figure2.5 Regulated Termination for Ultra SCSI

          55
      • 2.2.14 Select/Reselect During Selection/Reselection

        55
      • 2.2.15 Synchronous Operation

        56
        • Figure2.6 Determining the Synchronous Transfer Rate

          57
      • 2.2.16 Interrupt Handling

        59
      • 2.2.17 Chained Block Moves

        66
        • Figure2.7 Block Move and Chained Block Move Instructions

          67
    • 2.3 Parallel ROM Interface

      70
      • Table 2.6 Parallel ROM Support

        71
    • 2.4 Serial EEPROM Interface

      72
      • 2.4.1 Default Download Mode

        72
        • Table 2.7 Mode A Serial EEPROM Data Format

          73
      • 2.4.2 No Download Mode

        73
    • 2.5 Power Management

      73
      • Table 2.8 Power States

        74
      • 2.5.1 Power State D0

        74
      • 2.5.2 Power State D1

        74
      • 2.5.3 Power State D2

        75
      • 2.5.4 Power State D3

        75
  • Chapter3 Signal Descriptions

    77
    • 3.1 LSI53C875A Functional Signal Grouping

      78
      • Figure3.1 LSI53C875A Functional Signal Grouping

        78
    • 3.2 Signal Descriptions

      79
      • 3.2.1 Internal Pull-ups on LSI53C875A Signals

        79
        • Table 3.1 LSI53C875A Internal Pull-ups

          79
    • 3.3 PCI Bus Interface Signals

      80
      • 3.3.1 System Signals

        80
        • Table 3.2 System Signals

          80
      • 3.3.2 Address and Data Signals

        81
        • Table 3.3 Address and Data Signals

          81
      • 3.3.3 Interface Control Signals

        82
        • Table 3.4 Interface Control Signals

          82
      • 3.3.4 Arbitration Signals

        83
        • Table 3.5 Arbitration Signals

          83
      • 3.3.5 Error Reporting Signals

        83
        • Table 3.6 Error Reporting Signals

          83
      • 3.3.6 Interrupt Signal

        84
        • Table 3.7 Interrupt Signal

          84
    • 3.4 SCSI Bus Interface Signals

      84
      • 3.4.1 SCSI Bus Interface Signal

        84
        • Table 3.8 SCSI Bus Interface Signal

          84
      • 3.4.2 SCSI Signals

        85
        • Table 3.9 SCSI Signals

          85
      • 3.4.3 SCSI Control Signals

        85
        • Table 3.10 SCSI Control Signals

          85
    • 3.5 GPIO Signals

      86
      • Table 3.11 GPIO Signals

        86
    • 3.6 ROM Flash and Memory Interface Signals

      87
      • Table 3.12 ROM Flash and Memory Interface Signals

        87
    • 3.7 Test Interface Signals

      88
      • Table 3.13 Test Interface Signals

        88
    • 3.8 Power and Ground Signals

      89
      • Table 3.14 Power and Ground Signals

        89
    • 3.9 MAD Bus Programming

      90
      • Table 3.15 Decode of MAD Pins

        90
  • Chapter4 Registers

    93
    • 4.1 PCI Configuration Registers

      93
      • Table 4.1 PCI Configuration Register Map

        94
    • 4.2 SCSI Registers

      110
      • Table 4.2 SCSI Register Address Map

        111
      • Table 4.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1

        124
      • Table 4.4 Example Transfer Periods and Rates for Fast SCSI-2 and Ultra SCSI

        125
      • Table 4.5 Maximum Synchronous Offset

        126
      • Table 4.6 SCSI Synchronous Data FIFO Word Count

        136
    • 4.3 64-Bit SCRIPTS Selectors

      191
    • 4.4 Phase Mismatch Jump Registers

      195
  • Chapter5 SCSI SCRIPTS Instruction Set

    201
    • 5.1 Low Level Register Interface Mode

      201
    • 5.2 High Level SCSI SCRIPTS Mode

      202
      • Table 5.1 SCRIPTS Instructions

        203
      • 5.2.1 Sample Operation

        203
        • Figure5.1 SCRIPTS Overview

          205
    • 5.3 Block Move Instruction

      206
      • 5.3.1 First Dword

        206
        • Table 5.2 SCSI Information Transfer Phase

          212
      • 5.3.2 Second Dword

        213
    • 5.4 I/O Instruction

      213
      • 5.4.1 First Dword

        214
      • 5.4.2 Second Dword

        221
    • 5.5 Read/Write Instructions

      222
      • 5.5.1 First Dword

        222
      • 5.5.2 Second Dword

        223
      • 5.5.3 Read-Modify-Write Cycles

        223
      • 5.5.4 Move To/From SFBR Cycles

        224
        • Table 5.3 Read/Write Instructions

          224
    • 5.6 Transfer Control Instructions

      225
      • 5.6.1 First Dword

        226
        • Table 5.4 Transfer Control Instructions

          226
        • Table 5.5 SCSI Phase Comparisons

          229
      • 5.6.2 Second Dword

        232
    • 5.7 Memory Move Instructions

      232
      • 5.7.1 First Dword

        233
      • 5.7.2 Read/Write System Memory from SCRIPTS

        234
      • 5.7.3 Second Dword

        234
      • 5.7.4 Third Dword

        235
    • 5.8 Load and Store Instructions

      235
      • 5.8.1 First Dword

        236
      • 5.8.2 Second Dword

        237
  • Chapter6 Electrical Specifications

    239
    • 6.1 DC Characteristics

      239
      • Table 6.1 Absolute Maximum Stress Ratings

        240
      • Table 6.2 Operating Conditions

        240
      • Table 6.3 Input Capacitance

        240
      • Table 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/

        241
      • Table 6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4]

        241
      • Table 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...

        242
      • Table 6.7 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/

        242
      • Table 6.8 Output Signal—TDO

        242
      • Table 6.9 Output Signals—IRQ/, MAC/_TESTOUT, REQ/

        243
      • Table 6.10 Output Signal—SERR/

        243
    • 6.2 TolerANT Technology Electrical Characteristics

      243
      • Table 6.11 TolerANT Technology Electrical Characteristics for SE SCSI Signals

        244
      • Figure6.1 Rise and Fall Time Test Condition

        245
      • Figure6.2 SCSI Input Filtering

        245
      • Figure6.3 Hysteresis of SCSI Receivers

        245
      • Figure6.4 Input Current as a Function of Input Voltage

        246
      • Figure6.5 Output Current as a Function of Output Voltage

        246
    • 6.3 AC Characteristics

      247
      • Table 6.12 External Clock

        247
      • Figure6.6 External Clock

        247
      • Table 6.13 Reset Input

        248
      • Figure6.7 Reset Input

        248
      • Table 6.14 Interrupt Output

        248
      • Figure6.8 Interrupt Output

        249
    • 6.4 PCI and External Memory Interface Timing Diagrams

      249
      • 6.4.1 Target Timing

        251
        • Table 6.15 PCI Configuration Register Read

          251
        • Figure6.9 PCI Configuration Register Read

          251
        • Table 6.16 PCI Configuration Register Write

          252
        • Figure6.10 PCI Configuration Register Write

          252
        • Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read

          253
        • Figure6.11 32-Bit Operating Register/SCRIPTS RAM Read

          253
        • Table 6.18 64-Bit Address Operating Register/SCRIPTS RAM Read

          254
        • Figure6.12 64-Bit Address Operating Register/SCRIPTS RAM Read

          254
        • Table 6.19 32-Bit Operating Register/SCRIPTS RAM Write

          255
        • Figure6.13 32-Bit Operating Register/SCRIPTS RAM Write

          255
        • Table 6.20 64-Bit Address Operating Register/SCRIPTS RAM Write

          256
        • Figure6.14 64-Bit Address Operating Register/SCRIPTS RAM Write

          256
      • 6.4.2 Initiator Timing

        257
        • Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data

          257
        • Figure6.15 Nonburst Opcode Fetch, 32-Bit Address and Data

          258
        • Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data

          259
        • Figure6.16 Burst Opcode Fetch, 32-Bit Address and Data

          260
        • Table 6.23 Back-to-Back Read, 32-Bit Address and Data

          261
        • Figure6.17 Back-to-Back Read, 32-Bit Address and Data

          262
        • Table 6.24 Back-to-Back Write, 32-Bit Address and Data

          263
        • Figure6.18 Back-to-Back Write, 32-Bit Address and Data

          264
        • Table 6.25 Burst Read, 32-Bit Address and Data

          265
        • Figure6.19 Burst Read, 32-Bit Address and Data

          266
        • Table 6.26 Burst Read, 64-Bit Address and Data

          267
        • Figure6.20 Burst Read, 64-Bit Address and Data

          268
        • Table 6.27 Burst Write, 32-Bit Address and Data

          269
        • Figure6.21 Burst Write, 32-Bit Address and Data

          270
        • Table 6.28 Burst Write, 64-Bit Address and 32-Bit Data

          271
        • Figure6.22 Burst Write, 64-Bit Address and 32-Bit Data

          272
      • 6.4.3 External Memory Timing

        273
        • Table 6.29 External Memory Read

          273
        • Figure6.23 External Memory Read

          274
        • Table 6.30 External Memory Write

          276
        • Figure6.24 External Memory Write

          278
        • Table 6.31 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle

          280
        • Figure6.25 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle

          280
        • Table 6.32 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle

          281
        • Figure6.26 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle

          281
        • Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle

          282
        • Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle

          284
        • Table 6.33 Slow Memory (£ 128 Kbytes) Read Cycle

          286
        • Figure6.29 Slow Memory (£ 128 Kbytes) Read Cycle

          286
        • Table 6.34 Slow Memory (£ 128 Kbytes) Write Cycle

          287
        • Figure6.30 Slow Memory (£ 128 Kbytes) Write Cycle

          287
        • Table 6.35 £ 64 Kbytes ROM Read Cycle

          288
        • Figure6.31 £ 64 Kbytes ROM Read Cycle

          288
        • Table 6.36 £ 64 Kbyte ROM Write Cycle

          289
        • Figure6.32 £ 64 Kbyte ROM Write Cycle

          289
    • 6.5 SCSI Timing Diagrams

      290
      • Table 6.37 Initiator Asynchronous Send

        290
      • Figure6.33 Initiator Asynchronous Send

        290
      • Table 6.38 Initiator Asynchronous Receive

        291
      • Figure6.34 Initiator Asynchronous Receive

        291
      • Table 6.39 Target Asynchronous Send

        292
      • Figure6.35 Target Asynchronous Send

        292
      • Table 6.40 Target Asynchronous Receive

        293
      • Figure6.36 Target Asynchronous Receive

        293
      • Table 6.41 SCSI-1 Transfers (5.0 Mbytes)

        293
      • Table 6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...

        294
      • Table 6.43 Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Q...

        294
      • Figure6.37 Initiator and Target Synchronous Transfer

        295
    • 6.6 Package Diagrams

      296
      • Figure6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing

        296
      • Table6.44 160 PQFP Pin List by Location

        298
      • Figure6.39 169-Pin BGA Mechanical Drawing

        299
      • Table6.45 169 BGA Pin List by Location

        300
  • AppendixA Register Summary

    301
    • TableA.1 LSI53C875A PCI Register Map

      301
    • TableA.2 LSI53C875A SCSI Register Map

      302
  • AppendixB External Memory Interface Diagram Examples

    307
    • FigureB.1 16 Kbyte Interface with 200 ns Memory

      307
    • FigureB.2 64 Kbyte Interface with 150 ns Memory

      308
    • FigureB.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory

      309
    • FigureB.4 512 Kbyte Interface with 150 ns Memory

      310
  • Index

    311
  • Customer Feedback

    321