用户手册目录LSI53C875A PCI to Ultra SCSI1Controller1Chapter1 General Description15Figure1.1 Typical LSI53C875A System Application16Figure1.2 Typical LSI53C875A Board Application161.1 New Features in the LSI53C875A171.2 Benefits of Ultra SCSI171.3 TolerANT® Technology181.4 LSI53C875A Benefits Summary181.4.1 SCSI Performance191.4.2 PCI Performance201.4.3 Integration201.4.4 Ease of Use201.4.5 Flexibility211.4.6 Reliability221.4.7 Testability22Chapter2 Functional Description23Figure2.1 LSI53C875A Block Diagram242.1 PCI Functional Description242.1.1 PCI Addressing242.1.2 PCI Bus Commands and Functions Supported25Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C875A262.1.3 PCI Cache Mode31Table 2.2 PCI Cache Mode Alignment342.2 SCSI Functional Description382.2.1 SCRIPTS Processor392.2.2 Internal SCRIPTS RAM402.2.3 64-Bit Addressing in SCRIPTS412.2.4 Hardware Control of SCSI Activity LED412.2.5 Designing an Ultra SCSI System422.2.6 Prefetching SCRIPTS Instructions432.2.7 Opcode Fetch Burst Capability442.2.8 Load and Store Instructions442.2.9 JTAG Boundary Scan Testing452.2.10 SCSI Loopback Mode452.2.11 Parity Options46Table 2.3 Bits Used for Parity Control and Generation47Table 2.4 SCSI Parity Control48Table 2.5 SCSI Parity Errors and Interrupts48Figure2.2 Parity Checking/Generation492.2.12 DMA FIFO49Figure2.3 DMA FIFO Sections50Figure2.4 LSI53C875A Host Interface SCSI Data Paths512.2.13 SCSI Bus Interface54Figure2.5 Regulated Termination for Ultra SCSI552.2.14 Select/Reselect During Selection/Reselection552.2.15 Synchronous Operation56Figure2.6 Determining the Synchronous Transfer Rate572.2.16 Interrupt Handling592.2.17 Chained Block Moves66Figure2.7 Block Move and Chained Block Move Instructions672.3 Parallel ROM Interface70Table 2.6 Parallel ROM Support712.4 Serial EEPROM Interface722.4.1 Default Download Mode72Table 2.7 Mode A Serial EEPROM Data Format732.4.2 No Download Mode732.5 Power Management73Table 2.8 Power States742.5.1 Power State D0742.5.2 Power State D1742.5.3 Power State D2752.5.4 Power State D375Chapter3 Signal Descriptions773.1 LSI53C875A Functional Signal Grouping78Figure3.1 LSI53C875A Functional Signal Grouping783.2 Signal Descriptions793.2.1 Internal Pull-ups on LSI53C875A Signals79Table 3.1 LSI53C875A Internal Pull-ups793.3 PCI Bus Interface Signals803.3.1 System Signals80Table 3.2 System Signals803.3.2 Address and Data Signals81Table 3.3 Address and Data Signals813.3.3 Interface Control Signals82Table 3.4 Interface Control Signals823.3.4 Arbitration Signals83Table 3.5 Arbitration Signals833.3.5 Error Reporting Signals83Table 3.6 Error Reporting Signals833.3.6 Interrupt Signal84Table 3.7 Interrupt Signal843.4 SCSI Bus Interface Signals843.4.1 SCSI Bus Interface Signal84Table 3.8 SCSI Bus Interface Signal843.4.2 SCSI Signals85Table 3.9 SCSI Signals853.4.3 SCSI Control Signals85Table 3.10 SCSI Control Signals853.5 GPIO Signals86Table 3.11 GPIO Signals863.6 ROM Flash and Memory Interface Signals87Table 3.12 ROM Flash and Memory Interface Signals873.7 Test Interface Signals88Table 3.13 Test Interface Signals883.8 Power and Ground Signals89Table 3.14 Power and Ground Signals893.9 MAD Bus Programming90Table 3.15 Decode of MAD Pins90Chapter4 Registers934.1 PCI Configuration Registers93Table 4.1 PCI Configuration Register Map944.2 SCSI Registers110Table 4.2 SCSI Register Address Map111Table 4.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1124Table 4.4 Example Transfer Periods and Rates for Fast SCSI-2 and Ultra SCSI125Table 4.5 Maximum Synchronous Offset126Table 4.6 SCSI Synchronous Data FIFO Word Count1364.3 64-Bit SCRIPTS Selectors1914.4 Phase Mismatch Jump Registers195Chapter5 SCSI SCRIPTS Instruction Set2015.1 Low Level Register Interface Mode2015.2 High Level SCSI SCRIPTS Mode202Table 5.1 SCRIPTS Instructions2035.2.1 Sample Operation203Figure5.1 SCRIPTS Overview2055.3 Block Move Instruction2065.3.1 First Dword206Table 5.2 SCSI Information Transfer Phase2125.3.2 Second Dword2135.4 I/O Instruction2135.4.1 First Dword2145.4.2 Second Dword2215.5 Read/Write Instructions2225.5.1 First Dword2225.5.2 Second Dword2235.5.3 Read-Modify-Write Cycles2235.5.4 Move To/From SFBR Cycles224Table 5.3 Read/Write Instructions2245.6 Transfer Control Instructions2255.6.1 First Dword226Table 5.4 Transfer Control Instructions226Table 5.5 SCSI Phase Comparisons2295.6.2 Second Dword2325.7 Memory Move Instructions2325.7.1 First Dword2335.7.2 Read/Write System Memory from SCRIPTS2345.7.3 Second Dword2345.7.4 Third Dword2355.8 Load and Store Instructions2355.8.1 First Dword2365.8.2 Second Dword237Chapter6 Electrical Specifications2396.1 DC Characteristics239Table 6.1 Absolute Maximum Stress Ratings240Table 6.2 Operating Conditions240Table 6.3 Input Capacitance240Table 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/241Table 6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4]241Table 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...242Table 6.7 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/242Table 6.8 Output Signal—TDO242Table 6.9 Output Signals—IRQ/, MAC/_TESTOUT, REQ/243Table 6.10 Output Signal—SERR/2436.2 TolerANT Technology Electrical Characteristics243Table 6.11 TolerANT Technology Electrical Characteristics for SE SCSI Signals244Figure6.1 Rise and Fall Time Test Condition245Figure6.2 SCSI Input Filtering245Figure6.3 Hysteresis of SCSI Receivers245Figure6.4 Input Current as a Function of Input Voltage246Figure6.5 Output Current as a Function of Output Voltage2466.3 AC Characteristics247Table 6.12 External Clock247Figure6.6 External Clock247Table 6.13 Reset Input248Figure6.7 Reset Input248Table 6.14 Interrupt Output248Figure6.8 Interrupt Output2496.4 PCI and External Memory Interface Timing Diagrams2496.4.1 Target Timing251Table 6.15 PCI Configuration Register Read251Figure6.9 PCI Configuration Register Read251Table 6.16 PCI Configuration Register Write252Figure6.10 PCI Configuration Register Write252Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read253Figure6.11 32-Bit Operating Register/SCRIPTS RAM Read253Table 6.18 64-Bit Address Operating Register/SCRIPTS RAM Read254Figure6.12 64-Bit Address Operating Register/SCRIPTS RAM Read254Table 6.19 32-Bit Operating Register/SCRIPTS RAM Write255Figure6.13 32-Bit Operating Register/SCRIPTS RAM Write255Table 6.20 64-Bit Address Operating Register/SCRIPTS RAM Write256Figure6.14 64-Bit Address Operating Register/SCRIPTS RAM Write2566.4.2 Initiator Timing257Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data257Figure6.15 Nonburst Opcode Fetch, 32-Bit Address and Data258Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data259Figure6.16 Burst Opcode Fetch, 32-Bit Address and Data260Table 6.23 Back-to-Back Read, 32-Bit Address and Data261Figure6.17 Back-to-Back Read, 32-Bit Address and Data262Table 6.24 Back-to-Back Write, 32-Bit Address and Data263Figure6.18 Back-to-Back Write, 32-Bit Address and Data264Table 6.25 Burst Read, 32-Bit Address and Data265Figure6.19 Burst Read, 32-Bit Address and Data266Table 6.26 Burst Read, 64-Bit Address and Data267Figure6.20 Burst Read, 64-Bit Address and Data268Table 6.27 Burst Write, 32-Bit Address and Data269Figure6.21 Burst Write, 32-Bit Address and Data270Table 6.28 Burst Write, 64-Bit Address and 32-Bit Data271Figure6.22 Burst Write, 64-Bit Address and 32-Bit Data2726.4.3 External Memory Timing273Table 6.29 External Memory Read273Figure6.23 External Memory Read274Table 6.30 External Memory Write276Figure6.24 External Memory Write278Table 6.31 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle280Figure6.25 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle280Table 6.32 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle281Figure6.26 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle281Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle282Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle284Table 6.33 Slow Memory (£ 128 Kbytes) Read Cycle286Figure6.29 Slow Memory (£ 128 Kbytes) Read Cycle286Table 6.34 Slow Memory (£ 128 Kbytes) Write Cycle287Figure6.30 Slow Memory (£ 128 Kbytes) Write Cycle287Table 6.35 £ 64 Kbytes ROM Read Cycle288Figure6.31 £ 64 Kbytes ROM Read Cycle288Table 6.36 £ 64 Kbyte ROM Write Cycle289Figure6.32 £ 64 Kbyte ROM Write Cycle2896.5 SCSI Timing Diagrams290Table 6.37 Initiator Asynchronous Send290Figure6.33 Initiator Asynchronous Send290Table 6.38 Initiator Asynchronous Receive291Figure6.34 Initiator Asynchronous Receive291Table 6.39 Target Asynchronous Send292Figure6.35 Target Asynchronous Send292Table 6.40 Target Asynchronous Receive293Figure6.36 Target Asynchronous Receive293Table 6.41 SCSI-1 Transfers (5.0 Mbytes)293Table 6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...294Table 6.43 Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Q...294Figure6.37 Initiator and Target Synchronous Transfer2956.6 Package Diagrams296Figure6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing296Table6.44 160 PQFP Pin List by Location298Figure6.39 169-Pin BGA Mechanical Drawing299Table6.45 169 BGA Pin List by Location300AppendixA Register Summary301TableA.1 LSI53C875A PCI Register Map301TableA.2 LSI53C875A SCSI Register Map302AppendixB External Memory Interface Diagram Examples307FigureB.1 16 Kbyte Interface with 200 ns Memory307FigureB.2 64 Kbyte Interface with 150 ns Memory308FigureB.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory309FigureB.4 512 Kbyte Interface with 150 ns Memory310Index311Customer Feedback321文件大小： 2.5 MB页数： 328Language: English打开用户手册
