Intel IA-32 Manuale Utente

7-32 Vol. 3A

Entries in the TLBs are tagged with an ID that indicates the logical processor that initiated the
translation. This tag applies even for translations that are marked global using the page global
feature for memory paging. 

When a logical processor performs a TLB invalidation operation, only the TLB entries that are
tagged for that logical processor are flushed. This protocol applies to all TLB invalidation oper-
ations, including writes to control registers CR3 and CR4 and uses of the INVLPG instruction.

In an Intel Xeon processor MP, logical processors share the catastrophic shutdown detector and
the automatic thermal monitoring mechanism (see Section 13.4, “Thermal Monitoring and
Protection”). Sharing results in the following behavior:

•

If the processor’s core temperature rises above the preset catastrophic shutdown temper-
ature, the processor core halts execution, which causes both logical processors to stop
execution.

•

When the processor’s core temperature rises above the preset automatic thermal monitor
trip temperature, the clock speed of the processor core is automatically modulated, which
effects the execution speed of both logical processors.

For software controlled clock modulation, each logical processor has its own
IA32_CLOCK_MODULATION MSR, allowing clock modulation to be enabled or disabled on
a logical processor basis. Typically, if software controlled clock modulation is going to be used,
the feature must be enabled for all the logical processors within a physical processor and the
modulation duty cycle must be set to the same value for each logical processor. If the duty cycle
values differ between the logical processors, the processor clock will be modulated at the highest
duty cycle selected.

This section describes the constraints on external signals received through the pins of an Intel
Xeon processor MP and how these signals are shared between its logical processors.

•

STPCLK# — A single STPCLK# pin is provided on the physical package of the Intel
Xeon processor MP. External control logic uses this pin for power management within the
system. When the STPCLK# signal is asserted, the processor core transitions to the stop-
grant state, where instruction execution is halted but the processor core continues to
respond to snoop transactions. Regardless of whether the logical processors are active or
halted when the STPCLK# signal is asserted, execution is stopped on both logical
processors and neither will respond to interrupts.

In MP systems, the STPCLK# pins on all physical processors are generally tied together.
As a result this signal affects all the logical processors within the system simultaneously.

•

LINT0 and LINT1 pins — An Intel Xeon processor MP has only one set of LINT0 and
LINT1 pins, which are shared between the logical processors. When one of these pins is
asserted, both logical processors respond unless the pin has been masked in the APIC local