Intel IA-32 Manuale Utente
Vol. 3A 7-33
MULTIPLE-PROCESSOR MANAGEMENT
vector tables for one or both of the logical processors.
Typically in MP systems, the LINT0 and LINT1 pins are not used to deliver interrupts to
the logical processors. Instead all interrupts are delivered to the local processors through
the I/O APIC.
the logical processors. Instead all interrupts are delivered to the local processors through
the I/O APIC.
•
A20M# pin — On an IA-32 processor, the A20M# pin is typically provided for compati-
bility with the Intel 286 processor. Asserting this pin causes bit 20 of the physical address
to be masked (forced to zero) for all external bus memory accesses. The Intel Xeon
processor MP provides one A20M# pin, which affects the operation of both logical
processors within the physical processor. This configuration is compatible with the IA-32
architecture.
bility with the Intel 286 processor. Asserting this pin causes bit 20 of the physical address
to be masked (forced to zero) for all external bus memory accesses. The Intel Xeon
processor MP provides one A20M# pin, which affects the operation of both logical
processors within the physical processor. This configuration is compatible with the IA-32
architecture.
7.9
DUAL-CORE ARCHITECTURE
This section describes the architecture of dual-core IA-32 processors. The discussion is appli-
cable to the Intel Pentium processor Extreme Edition and Pentium D and Dual-core Intel Xeon
processor. Features vary across different microarchitectures and are detectable using CPUID.
cable to the Intel Pentium processor Extreme Edition and Pentium D and Dual-core Intel Xeon
processor. Features vary across different microarchitectures and are detectable using CPUID.
In general, each processor core has dedicated microarchitectural resources identical to a single-
processor implementation of the underlying microarchitecture without hardware multi-
threading capability. Each logical processor in a dual-core IA-32 processor (whether supporting
Hyper-Threading Technology or not) has its own APIC functionality, PAT, machine check archi-
tecture, debug registers and extensions. Each logical processor handles serialization instructions
or self-modifying code on its own. Memory order is handled the same way as in Hyper-
Threading Technology.
processor implementation of the underlying microarchitecture without hardware multi-
threading capability. Each logical processor in a dual-core IA-32 processor (whether supporting
Hyper-Threading Technology or not) has its own APIC functionality, PAT, machine check archi-
tecture, debug registers and extensions. Each logical processor handles serialization instructions
or self-modifying code on its own. Memory order is handled the same way as in Hyper-
Threading Technology.
The topology of the cache hierarchy (with respect to whether a given cache level is shared by
one or more processor cores or by all logical processors in the physical package) depends on the
processor implementation. Software must use the deterministic cache parameter leaf of CPUID
instruction to discover the cache-sharing topology between the logical processors in a multi-
threading environment.
one or more processor cores or by all logical processors in the physical package) depends on the
processor implementation. Software must use the deterministic cache parameter leaf of CPUID
instruction to discover the cache-sharing topology between the logical processors in a multi-
threading environment.
7.9.1
Logical Processor Support
The topological composition of processor cores and logical processors in a multi-core IA-32
architecture processor can be discovered using CPUID. Within each processor core, one or more
logical processors may be available.
architecture processor can be discovered using CPUID. Within each processor core, one or more
logical processors may be available.
System software must follow the requirement MP initialization sequences (see Section 7.5,
“Multiple-Processor (MP) Initialization”) to recognize and enable logical processors. At
runtime, software can enumerate those logical processors enabled by system software to identify
the topological relationships between these logical processors. (See Section 7.10.4, “Identifying
Topological Relationships in a MP System”).
“Multiple-Processor (MP) Initialization”) to recognize and enable logical processors. At
runtime, software can enumerate those logical processors enabled by system software to identify
the topological relationships between these logical processors. (See Section 7.10.4, “Identifying
Topological Relationships in a MP System”).