Intel IA-32 Manuale Utente
Vol. 3A 7-45
MULTIPLE-PROCESSOR MANAGEMENT
If ((PackageID[ProcessorNum] | CoreID[ProcessorNum]) == CoreIDBucket[i]) {
CoreProcessorMask[i] |= ProcessorMask;
Break; // found in existing bucket, skip to next iteration
Break; // found in existing bucket, skip to next iteration
}
}
if (i == CoreNum) {
if (i == CoreNum) {
//Did not match any bucket, start new bucket
CoreIDBucket[i] = PackageID[ProcessorNum] | CoreID[ProcessorNum];
CoreProcessorMask[i] = ProcessorMask;
CoreNum++;
CoreIDBucket[i] = PackageID[ProcessorNum] | CoreID[ProcessorNum];
CoreProcessorMask[i] = ProcessorMask;
CoreNum++;
}
}
// CoreNum has the number of cores started in the OS
// CoreProcessorMask[] array has the processor set of each core
// CoreNum has the number of cores started in the OS
// CoreProcessorMask[] array has the processor set of each core
Other processor relationships such as processor mask of sibling cores can be computed from set
operations of the PackageProcessorMask[] and CoreProcessorMask[].
operations of the PackageProcessorMask[] and CoreProcessorMask[].
The algorithm shown above can be applied to earlier generations of single-core IA-32 proces-
sors that support Hyper-Threading Technology and in the situation that the deterministic cache
parameter leaf is not supported. This is handled by ensuring MaxCoresPerPackage() return 1 in
those situations.
sors that support Hyper-Threading Technology and in the situation that the deterministic cache
parameter leaf is not supported. This is handled by ensuring MaxCoresPerPackage() return 1 in
those situations.
7.11
MANAGEMENT OF IDLE AND BLOCKED CONDITIONS
During execution of an IA-32 processor supporting Hyper-Threading Technology with each
logical processor actively executing a thread, logical processors use shared processor resources
(cache lines, TLB entries, and bus accesses) on an as-needed basis. When one logical processor
is idle (no work to do) or blocked (on a lock or semaphore), additional management of the core
execution engine resource can be accomplished by using the HLT (halt), PAUSE, or the
MONITOR/MWAIT instructions.
logical processor actively executing a thread, logical processors use shared processor resources
(cache lines, TLB entries, and bus accesses) on an as-needed basis. When one logical processor
is idle (no work to do) or blocked (on a lock or semaphore), additional management of the core
execution engine resource can be accomplished by using the HLT (halt), PAUSE, or the
MONITOR/MWAIT instructions.
7.11.1
HLT Instruction
The HLT instruction stops the execution of the logical processor on which it is executed and
places it in a halted state until further notice (see the description of the HLT instruction in
Chapter 3, “Instruction Set Reference, A-M,” of the IA-32 Intel® Architecture Software Devel-
oper’s Manual, Volume 2A). When a logical processor is halted, active logical processors
continue to have full access to the shared resources within the physical package. Here shared
resources that were being used by the halted logical processor become available to active logical
processors, allowing them to execute at greater efficiency. When the halted logical processor
resumes execution, shared resources are again shared among all active logical processors. (See
Section 7.11.6.3, “Halt Idle Logical Processors,” for more information about using the HLT
instruction with IA-32 processors supporting Hyper-Threading Technology.)
places it in a halted state until further notice (see the description of the HLT instruction in
Chapter 3, “Instruction Set Reference, A-M,” of the IA-32 Intel® Architecture Software Devel-
oper’s Manual, Volume 2A). When a logical processor is halted, active logical processors
continue to have full access to the shared resources within the physical package. Here shared
resources that were being used by the halted logical processor become available to active logical
processors, allowing them to execute at greater efficiency. When the halted logical processor
resumes execution, shared resources are again shared among all active logical processors. (See
Section 7.11.6.3, “Halt Idle Logical Processors,” for more information about using the HLT
instruction with IA-32 processors supporting Hyper-Threading Technology.)