Intel IA-32 Manuale Utente
8-10 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.4.3
Enabling or Disabling the Local APIC
The local APIC can be enabled or disabled in either of two ways:
1.
Using the APIC global enable/disable flag in the IA32_APIC_BASE MSR (MSR address
1BH; see Figure 8-5):
1BH; see Figure 8-5):
— When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an
IA-32 processor without an on-chip APIC. The CPUID feature flag for the APIC (see
Section 8.4.2, “Presence of the Local APIC”) is also set to 0.
Section 8.4.2, “Presence of the Local APIC”) is also set to 0.
— When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wire APIC
bus cannot be generally re-enabled until a system hardware reset. The 3-wire bus
looses track of arbitration that would be necessary for complete re-enabling. Certain
APIC functionality can be enabled (for example: performance and thermal monitoring
interrupt generation).
looses track of arbitration that would be necessary for complete re-enabling. Certain
APIC functionality can be enabled (for example: performance and thermal monitoring
interrupt generation).
— For processors that use Front Side Bus (FSB) delivery of interrupts, software may
disable or enable the APIC by setting and resetting IA32_APIC_BASE[11]. A
hardware reset is not required to re-start APIC functionality.
hardware reset is not required to re-start APIC functionality.
— When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC may be lost
and the APIC may return to the state described in Section 8.4.7.1, “Local APIC State
After Power-Up or Reset.”
After Power-Up or Reset.”
2.
Using the APIC software enable/disable flag in the spurious-interrupt vector register (see
Figure 8-23):
Figure 8-23):
— If IA32_APIC_BASE[11] is 1, software can temporarily disable a local APIC at any
time by clearing the APIC software enable/disable flag in the spurious-interrupt vector
register (see Figure 8-23). The state of the local APIC when in this software-disabled
state is described in Section 8.4.7.2, “Local APIC State After It Has Been Software
Disabled.”
register (see Figure 8-23). The state of the local APIC when in this software-disabled
state is described in Section 8.4.7.2, “Local APIC State After It Has Been Software
Disabled.”
— When the local APIC is in the software-disabled state, it can be re-enabled at any time
by setting the APIC software enable/disable flag to 1.
For the Pentium processor, the APICEN pin (which is shared with the PICD1 pin) is used during
power-up or RESET to disable the local APIC.
power-up or RESET to disable the local APIC.
Note that each entry in the LVT has a mask bit that can be used to inhibit interrupts from being
delivered to the processor from selected local interrupt sources (the LINT0 and LINT1 pins, the
APIC timer, the performance-monitoring counters, the thermal sensor, and/or the internal APIC
error detector).
delivered to the processor from selected local interrupt sources (the LINT0 and LINT1 pins, the
APIC timer, the performance-monitoring counters, the thermal sensor, and/or the internal APIC
error detector).