Intel IA-32 Manuale Utente
Vol. 3A 8-15
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.5
HANDLING LOCAL INTERRUPTS
The following sections describe facilities that are provided in the local APIC for handling local
interrupts. These include: the processor’s LINT0 and LINT1 pins, the APIC timer, the perfor-
mance-monitoring counters, the thermal sensor, and the internal APIC error detector. Local
interrupt handling facilities include: the LVT, the error status register (ESR), the divide config-
uration register (DCR), and the initial count and current count registers.
interrupts. These include: the processor’s LINT0 and LINT1 pins, the APIC timer, the perfor-
mance-monitoring counters, the thermal sensor, and the internal APIC error detector. Local
interrupt handling facilities include: the LVT, the error status register (ESR), the divide config-
uration register (DCR), and the initial count and current count registers.
8.5.1
Local Vector Table
The local vector table (LVT) allows software to specify the manner in which the local interrupts
are delivered to the processor core. It consists of the following five 32-bit APIC registers (see
Figure 8-8), one for each local interrupt:
are delivered to the processor core. It consists of the following five 32-bit APIC registers (see
Figure 8-8), one for each local interrupt:
•
LVT Timer Register (FEE0 0320H) — Specifies interrupt delivery when the APIC timer
signals an interrupt (see Section 8.5.4, “APIC Timer”).
signals an interrupt (see Section 8.5.4, “APIC Timer”).
•
LVT Thermal Monitor Register (FEE0 0330H) — Specifies interrupt delivery when the
thermal sensor generates an interrupt (see Section 13.4.2, “Thermal Monitor”). This LVT
entry is implementation specific, not architectural. If implemented, it will always be at
base address FEE0 0330H.
thermal sensor generates an interrupt (see Section 13.4.2, “Thermal Monitor”). This LVT
entry is implementation specific, not architectural. If implemented, it will always be at
base address FEE0 0330H.
•
LVT Performance Counter Register (FEE0 0340H) — Specifies interrupt delivery
when a performance counter generates an interrupt on overflow (see Section 18.13.6.9,
“Generating an Interrupt on Overflow”). This LVT entry is implementation specific, not
architectural. If implemented, it is not guaranteed to be at base address FEE0 0340H.
when a performance counter generates an interrupt on overflow (see Section 18.13.6.9,
“Generating an Interrupt on Overflow”). This LVT entry is implementation specific, not
architectural. If implemented, it is not guaranteed to be at base address FEE0 0340H.
•
LVT LINT0 Register (FEE0 0350H) — Specifies interrupt delivery when an interrupt is
signaled at the LINT0 pin.
signaled at the LINT0 pin.
•
LVT LINT1 Register (FEE0 0360H) — Specifies interrupt delivery when an interrupt is
signaled at the LINT1 pin.
signaled at the LINT1 pin.
•
LVT Error Register (FEE0 0370H) — Specifies interrupt delivery when the APIC
detects an internal error (see Section 8.5.3, “Error Handling”).
detects an internal error (see Section 8.5.3, “Error Handling”).
The LVT performance counter register and its associated interrupt were introduced in the P6
processors and are also present in the Pentium 4 and Intel Xeon processors. The LVT thermal
processors and are also present in the Pentium 4 and Intel Xeon processors. The LVT thermal
Figure 8-7. Local APIC Version Register
31
0
Reserved
23
24
15
Version
Max. LVT
Value after reset: 000N 00VVH
V = Version, N = # of LVT entries minus 1
V = Version, N = # of LVT entries minus 1
Entry
7
Address: FEE0 0030H
16
8
Reserved