Intel IA-32 Manuale Utente
Vol. 3A 8-13
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.4.7.1
Local APIC State After Power-Up or Reset
Following a power-up or RESET of the processor, the state of local APIC and its registers are
as follows:
as follows:
•
The following registers are reset to all 0s:
•
IRR, ISR, TMR, ICR, LDR, and TPR
•
Timer initial count and timer current count registers
•
Divide configuration register
•
The DFR register is reset to all 1s.
•
The LVT register is reset to 0s except for the mask bits; these are set to 1s.
•
The local APIC version register is not affected.
•
The local APIC ID register is set to a unique APIC ID. (Pentium and P6 family processors
only). The Arb ID register is set to the value in the APIC ID register.
only). The Arb ID register is set to the value in the APIC ID register.
•
The spurious-interrupt vector register is initialized to 000000FFH. By setting bit 8 to 0,
software disables the local APIC.
software disables the local APIC.
•
If the processor is the only processor in the system or it is the BSP in an MP system (see
Section 7.5.1, “BSP and AP Processors”); the local APIC will respond normally to INIT
and NMI messages, to INIT# signals and to STPCLK# signals. If the processor is in an MP
system and has been designated as an AP; the local APIC will respond the same as for the
BSP. In addition, it will respond to SIPI messages. For P6 family processors only, an AP
will not respond to a STPCLK# signal.
Section 7.5.1, “BSP and AP Processors”); the local APIC will respond normally to INIT
and NMI messages, to INIT# signals and to STPCLK# signals. If the processor is in an MP
system and has been designated as an AP; the local APIC will respond the same as for the
BSP. In addition, it will respond to SIPI messages. For P6 family processors only, an AP
will not respond to a STPCLK# signal.
8.4.7.2
Local APIC State After It Has Been Software Disabled
When the APIC software enable/disable flag in the spurious interrupt vector register has been
explicitly cleared (as opposed to being cleared during a power up or RESET), the local APIC is
temporarily disabled (see Section 8.4.3, “Enabling or Disabling the Local APIC”). The opera-
tion and response of a local APIC while in this software-disabled state is as follows:
explicitly cleared (as opposed to being cleared during a power up or RESET), the local APIC is
temporarily disabled (see Section 8.4.3, “Enabling or Disabling the Local APIC”). The opera-
tion and response of a local APIC while in this software-disabled state is as follows:
•
The local APIC will respond normally to INIT, NMI, SMI, and SIPI messages.
•
Pending interrupts in the IRR and ISR registers are held and require masking or handling
by the CPU.
by the CPU.
•
The local APIC can still issue IPIs. It is software’s responsibility to avoid issuing IPIs
through the IPI mechanism and the ICR register if sending interrupts through this
mechanism is not desired.
through the IPI mechanism and the ICR register if sending interrupts through this
mechanism is not desired.
•
The reception or transmission of any IPIs that are in progress when the local APIC is
disabled are completed before the local APIC enters the software-disabled state.
disabled are completed before the local APIC enters the software-disabled state.
•
The mask bits for all the LVT entries are set. Attempts to reset these bits will be ignored.
•
(For Pentium and P6 family processors) The local APIC continues to listen to all bus
messages in order to keep its arbitration ID synchronized with the rest of the system.
messages in order to keep its arbitration ID synchronized with the rest of the system.