Intel IA-32 Manuale Utente
8-40 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.8.5
Signaling Interrupt Servicing Completion
For all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the start-up, or INIT-
Deassert delivery mode, the interrupt handler must include a write to the end-of-interrupt (EOI)
register (see Figure 8-21). This write must occur at the end of the handler routine, sometime
before the IRET instruction. This action indicates that the servicing of the current interrupt is
complete and the local APIC can issue the next interrupt from the ISR.
Deassert delivery mode, the interrupt handler must include a write to the end-of-interrupt (EOI)
register (see Figure 8-21). This write must occur at the end of the handler routine, sometime
before the IRET instruction. This action indicates that the servicing of the current interrupt is
complete and the local APIC can issue the next interrupt from the ISR.
Upon receiving and EOI, the APIC clears the highest priority bit in the ISR and dispatches the
next highest priority interrupt to the processor. If the terminated interrupt was a level-triggered
interrupt, the local APIC also sends an end-of-interrupt message to all I/O APICs.
next highest priority interrupt to the processor. If the terminated interrupt was a level-triggered
interrupt, the local APIC also sends an end-of-interrupt message to all I/O APICs.
For future compatibility, the software is requested to issue the end-of-interrupt command by
writing a value of 0H into the EOI register.
writing a value of 0H into the EOI register.
8.8.6
Task Priority in IA-32e Mode
In IA-32e mode, operating systems can manage the 16 priority classes of external interrupts (see
Section 8.8.3, “Interrupt, Task, and Processor Priority”) explicitly using the task priority register
(TPR). Operating systems can use the TPR to temporarily block specific (low-priority) inter-
rupts from interrupting a high-priority task. This is done by loading TPR with a value corre-
sponding to the highest-priority interrupt that is to be blocked. For example:
Section 8.8.3, “Interrupt, Task, and Processor Priority”) explicitly using the task priority register
(TPR). Operating systems can use the TPR to temporarily block specific (low-priority) inter-
rupts from interrupting a high-priority task. This is done by loading TPR with a value corre-
sponding to the highest-priority interrupt that is to be blocked. For example:
•
Loading TPR with a value of 8(01000B) blocks all interrupts with a priority of 8 or less
while allowing all interrupts with a priority of nine or more to be recognized.
while allowing all interrupts with a priority of nine or more to be recognized.
•
Loading the TPR with zero enables all external interrupts.
•
Loading TPR with 0 (01111B) disables all external interrupts.
The TPR (shown in Figure 8-18) is cleared to 0 on reset. In 64-bit mode, software can read and
write the TPR using an alternate interface, MOV CR8 instruction. The new priority level is
established when the MOV CR8 instruction completes execution. Software does not need to
force serialization after loading the TPR using MOV CR8.
write the TPR using an alternate interface, MOV CR8 instruction. The new priority level is
established when the MOV CR8 instruction completes execution. Software does not need to
force serialization after loading the TPR using MOV CR8.
Use of the MOV CRn instruction requires a privilege level of 0. Programs running at privilege
level greater than 0 cannot read or write the TPR. An attempt to do so results in a general-protec-
tion exception, #GP(0). The TPR is abstracted from the interrupt controller (IC), which priori-
tizes and manages external interrupt delivery to the processor. The IC can be an external device,
such as an APIC or 8259. Typically, the IC provides a priority mechanism similar or identical to
level greater than 0 cannot read or write the TPR. An attempt to do so results in a general-protec-
tion exception, #GP(0). The TPR is abstracted from the interrupt controller (IC), which priori-
tizes and manages external interrupt delivery to the processor. The IC can be an external device,
such as an APIC or 8259. Typically, the IC provides a priority mechanism similar or identical to
Figure 8-21. EOI Register
31
0
Address: 0FEE0 00B0H
Value after reset: 0H
Value after reset: 0H