Intel IA-32 Manuale Utente
Vol. 3A 8-41
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
the TPR. The IC, however, is considered implementation-dependent with the under-lying
priority mechanisms subject to change. The CR8, by contrast, is part of the Intel EM64T archi-
tecture. Software can depend on this definition remaining unchanged.
priority mechanisms subject to change. The CR8, by contrast, is part of the Intel EM64T archi-
tecture. Software can depend on this definition remaining unchanged.
Figure 8-22 shows the layout of CR8; only the low four bits are used. The remaining 60 bits are
reserved and must be written with zeros. Failure to do this results in a general-protection excep-
tion, #GP(0).
reserved and must be written with zeros. Failure to do this results in a general-protection excep-
tion, #GP(0).
8.8.6.1
Interaction of Task Priorities between CR8 and APIC
The first implementation of Intel EM64T includes a local advanced programmable interrupt
controller (APIC) that is similar to the APIC used with previous IA-32 processors. Some aspects
of the local APIC affect the operation of the architecturally defined task priority register and the
programming interface using CR8.
controller (APIC) that is similar to the APIC used with previous IA-32 processors. Some aspects
of the local APIC affect the operation of the architecturally defined task priority register and the
programming interface using CR8.
Notable CR8 and APIC interactions are:
•
The processor powers up with the local APIC enabled.
•
The APIC must be enabled for CR8 to function as the TPR. Writes to CR8 are reflected
into the APIC Task Priority Register.
into the APIC Task Priority Register.
•
APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0. A read of CR8 returns a
64-bit value which is the value of TPR[bits 7:4], zero extended to 64 bits.
64-bit value which is the value of TPR[bits 7:4], zero extended to 64 bits.
There are no ordering mechanisms between direct updates of the APIC.TPR and CR8. Operating
software should implement either direct APIC TPR updates or CR8 style TPR updates but not
mix them. Software can use a serializing instruction (for example, CPUID) to serialize updates
between MOV CR8 and stores to the APIC.
software should implement either direct APIC TPR updates or CR8 style TPR updates but not
mix them. Software can use a serializing instruction (for example, CPUID) to serialize updates
between MOV CR8 and stores to the APIC.
8.9
SPURIOUS INTERRUPT
A special situation may occur when a processor raises its task priority to be greater than or equal
to the level of the interrupt for which the processor INTR signal is currently being asserted. If
at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked
(programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing
the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return
without an EOI.
to the level of the interrupt for which the processor INTR signal is currently being asserted. If
at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked
(programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing
the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return
without an EOI.
Figure 8-22. CR8 Register
63
0
Value after reset: 0H
3
4
Reserved