Intel IA-32 Manuale Utente
8-44 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
destination and message during device configuration, allocating one or more
non-shared messages to each MSI capable function.”
non-shared messages to each MSI capable function.”
The capabilities mechanism provided by the PCI Local Bus Specification is used to identify and
configure MSI capable PCI devices. Among other fields, this structure contains a Message Data
Register and a Message Address Register. To request service, the PCI device function writes the
contents of the Message Data Register to the address contained in the Message Address Register
(and the Message Upper Address register for 64-bit message addresses).
configure MSI capable PCI devices. Among other fields, this structure contains a Message Data
Register and a Message Address Register. To request service, the PCI device function writes the
contents of the Message Data Register to the address contained in the Message Address Register
(and the Message Upper Address register for 64-bit message addresses).
Section 8.11.1 and Section 8.11.2 provide layout details for the Message Address Register and
the Message Data Register. The operation issued by the device is a PCI write command to the
Message Address Register with the Message Data Register contents. The operation follows
semantic rules as defined for PCI write operations and is a DWORD operation.
the Message Data Register. The operation issued by the device is a PCI write command to the
Message Address Register with the Message Data Register contents. The operation follows
semantic rules as defined for PCI write operations and is a DWORD operation.
8.11.1
Message Address Register Format
The format of the Message Address Register (lower 32-bits) is shown in Figure 8-24.
Fields in the Message Address Register are as follows:
1.
Bits 31-20 — These bits contain a fixed value for interrupt messages (0FEEH). This value
locates interrupts at the 1-MByte area with a base address of 4G – 18M. All accesses to this
region are directed as interrupt messages. Care must to be taken to ensure that no other
device claims the region as I/O space.
locates interrupts at the 1-MByte area with a base address of 4G – 18M. All accesses to this
region are directed as interrupt messages. Care must to be taken to ensure that no other
device claims the region as I/O space.
2.
Destination ID — This field contains an 8-bit destination ID. It identifies the message’s
target processor(s). The destination ID corresponds to bits 63:56 of the I/O APIC
Redirection Table Entry if the IOAPIC is used to dispatch the interrupt to the processor(s).
target processor(s). The destination ID corresponds to bits 63:56 of the I/O APIC
Redirection Table Entry if the IOAPIC is used to dispatch the interrupt to the processor(s).
3.
Redirection hint indication (RH) — This bit indicates whether the message should be
directed to the processor with the lowest interrupt priority among processors that can
receive the interrupt.
directed to the processor with the lowest interrupt priority among processors that can
receive the interrupt.
•
When RH is 0, the interrupt is directed to the processor listed in the Destination ID
field.
field.
•
When RH is 1 and the physical destination mode is used, the Destination ID field
must not be set to 0xFF; it must point to a processor that is present and enabled to
receive the interrupt.
must not be set to 0xFF; it must point to a processor that is present and enabled to
receive the interrupt.
Figure 8-24. Layout of the MSI Message Address Register
31
20 19
12 11
4
3
2
1
0
0FEEH
Destination ID
Reserved
RH
DM
XX